Patents by Inventor Tetsuhiro GOTOU

Tetsuhiro GOTOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10409519
    Abstract: A computer system comprises: a host computer including a host memory and a plurality of host processors; a storage apparatus; and an interface device coupled to the host computer and the storage apparatus, the interface device including a plurality of communication processors, wherein the host computer is configured to create a first logical partition, which is a destination of dedicated allocation of a first host memory area which is a partial area of the host memory, at least one of the plurality of host processors, and at least one of the plurality of communication processors.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: September 10, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yuusaku Kiyota, Tetsuhiro Gotou, Yoshihiro Toyohara
  • Publication number: 20170277470
    Abstract: A computer system comprises: a host computer including a host memory and a plurality of host processors; a storage apparatus; and an interface device coupled to the host computer and the storage apparatus, the interface device including a plurality of communication processors, wherein the host computer is configured to create a first logical partition, which is a destination of dedicated allocation of a first host memory area which is a partial area of the host memory, at least one of the plurality of host processors, and at least one of the plurality of communication processors.
    Type: Application
    Filed: October 10, 2014
    Publication date: September 28, 2017
    Inventors: Yuusaku KIYOTA, Tetsuhiro GOTOU, Yoshihiro TOYOHARA
  • Patent number: 9740404
    Abstract: A control apparatus, which is configured to control a plurality of processors corresponding to a plurality of storage areas arranged at an interface for accessing the storage areas, comprises: an update unit configured to, in a case a command sequence including each command outputted to one of the storage areas is inputted, update, by each one of the processors, a load applied by a command currently being executed to the storage area corresponding to the processor; a selection unit configured to, for one command of the command sequence, based on a load applied by a command currently executed at the processor updated by the update unit, select a processor out of the processors as an allocation destination of the one command; and an output unit configured to output the one command to the processor selected by the selection unit.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 22, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Yusaku Kiyota, Tetsuhiro Gotou, Yoshihiro Toyohara
  • Publication number: 20160328348
    Abstract: This invention provides a computer that, on the basis of identifying information for virtual ports for virtual machines in logical partitions, allows per-virtual-machine access control for storage systems. Said computer, which connects to said storage systems, has the following: hardware resources including processors, physical memory, and an I/O adapter; and a first hypervisor that logically divides said hardware resources into one or more logical partitions. Upon receiving an instruction to issue an I/O command to a logical unit of a storage system from a first virtual machine in a first logical partition, the I/O adapter transmits, to said storage system, an I/O command containing first identifying information that identifies a first virtual port for the first virtual machine.
    Type: Application
    Filed: January 29, 2014
    Publication date: November 10, 2016
    Applicant: HITACHI, LTD.
    Inventors: Tooru IBA, Yoshihiro TOYOHARA, Naoki KUBOTA, Tetsuhiro GOTOU
  • Publication number: 20160018989
    Abstract: A control apparatus, which is configured to control a plurality of processors corresponding to a plurality of storage areas arranged at an interface for accessing the storage areas, comprises: an update unit configured to, in a case a command sequence including each command outputted to one of the storage areas is inputted, update, by each one of the processors, a load applied by a command currently being executed to the storage area corresponding to the processor; a selection unit configured to, for one command of the command sequence, based on a load applied by a command currently executed at the processor updated by the update unit, select a processor out of the processors as an allocation destination of the one command; and an output unit configured to output the one command to the processor selected by the selection unit.
    Type: Application
    Filed: May 31, 2013
    Publication date: January 21, 2016
    Inventors: Yusaku KIYOTA, Tetsuhiro GOTOU, Yoshihiro TOYOHARA