Abstract: Comprises a memory control unit which transmits and receives data to and from respective interface control units in accordance with access requests and also controls access to the memory and a buffer which temporarily stores data smaller than 64 B, wherein the memory control unit, during access to the memory, if the processing data to be processed is 64 B, accesses the memory by using the processing data or, if the processing data is data smaller than 64 B, stores the data smaller than 64 B in the buffer, subsequently, if the address of the new processing data which became the processing data is sequential to the address of the data smaller than 64 B stored in the buffer, combines the new processing data and the data of the buffer and, on condition that the combined processing data is 64 B data, writes the combined processing data in the memory.