Patents by Inventor Tetsuhiro Tanaka

Tetsuhiro Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12389636
    Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: August 12, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Akihisa Shimomura, Naoto Yamade, Tomoya Takeshita, Tetsuhiro Tanaka
  • Publication number: 20250212605
    Abstract: A display device according to an embodiment includes a substrate, a first bottom electrode disposed on the substrate and having a first end, a first insulating layer disposed on the first bottom electrode, a second bottom electrode disposed on the first insulating layer and overlapping the first bottom electrode in a plan view, a second insulating layer disposed on the second bottom electrode, and a transistor including an active layer disposed on the second insulating layer, the transistor further including a gate electrode overlapping the active layer, wherein the second bottom electrode overlaps the active layer in a plan view and has a second end adjacent to the first end, and the first end and the second end do not overlap in a plan view.
    Type: Application
    Filed: July 23, 2024
    Publication date: June 26, 2025
    Applicant: Samsung Display Co., LTD.
    Inventors: Jong Hwan CHA, Yun Sik JOO, Tetsuhiro TANAKA, Hong Joon MOON, Seok Je SEONG, June Whan CHOI
  • Patent number: 12336224
    Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: June 17, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Tetsuhiro Tanaka
  • Publication number: 20250151558
    Abstract: A display device includes a first active pattern disposed on a substrate, a first gate electrode disposed on the first active pattern, a second active pattern disposed on the first gate electrode, being electrically connected to the first gate electrode, and including an extension part extending in a first direction and a protrusion part protruding from the extension part in a second direction crossing the first direction, and a voltage line disposed on the second active pattern, extending in the first direction, and overlapping the protrusion part in an overlapping region. The voltage line contacts the protrusion part through a first contact, and the first contact entirely overlaps the overlapping region on a plane.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Applicant: Samsung Display Co., Ltd.
    Inventors: SEUNG-HWAN CHO, WONSUK CHOI, TETSUHIRO TANAKA, JIRYUN PARK, SEOKJE SEONG, SEUNGWOO SUNG, JISEON LEE
  • Publication number: 20250120126
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tetsuhiro TANAKA, Mitsuhiro ICHIJO, Toshiya ENDO, Akihisa SHIMOMURA, Yuji EGI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Publication number: 20250105229
    Abstract: A display device includes a transistor including an active layer disposed on a substrate and a gate electrode disposed on the active layer, a gate insulating layer disposed between the active layer and the gate electrode, and a first insulating layer disposed on the gate electrode. The first insulating layer may include a first layer covering the active layer, the gate insulating layer, and the gate electrode and including silicon oxide, a second layer disposed on the first layer and including silicon oxynitride, and a third layer disposed on the second layer and including silicon nitride.
    Type: Application
    Filed: April 12, 2024
    Publication date: March 27, 2025
    Applicant: Samsung Display Co., LTD.
    Inventors: Tetsuhiro TANAKA, Jin Seok OH, Chang Ha KWAK, Jung Yub SEO, Jung Hoon YOON, Jin Ho JEONG
  • Publication number: 20250063762
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Tetsuhiro TANAKA, Hirokazu WATANABE, Yuhei SATO, Yasumasa YAMANE, Daisuke MATSUBAYASHI
  • Patent number: 12213359
    Abstract: A display device includes a first active pattern disposed on a substrate, a first gate electrode disposed on the first active pattern, a second active pattern disposed on the first gate electrode, being electrically connected to the first gate electrode, and including an extension part extending in a first direction and a protrusion part protruding from the extension part in a second direction crossing the first direction, and a voltage line disposed on the second active pattern, extending in the first direction, and overlapping the protrusion part in an overlapping region. The voltage line contacts the protrusion part through a first contact, and the first contact entirely overlaps the overlapping region on a plane.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: January 28, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Hwan Cho, Wonsuk Choi, Tetsuhiro Tanaka, Jiryun Park, Seokje Seong, Seungwoo Sung, Jiseon Lee
  • Patent number: 12191399
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: January 7, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Mitsuhiro Ichijo, Toshiya Endo, Akihisa Shimomura, Yuji Egi, Sachiaki Tezuka, Shunpei Yamazaki
  • Publication number: 20240414939
    Abstract: A display device includes a pixel circuit disposed on a base layer and including a transistor including a source electrode, a drain electrode, a gate electrode, and a semiconductor layer, and a light emitting element electrically connected to the pixel circuit. The semiconductor layer includes a low concentration area, a high concentration area, and a slope concentration area between the low concentration area and the high concentration area, which are divided based on a concentration of a carrier and are spaced apart from each other in a length direction of the base layer. The low concentration area and a portion of the slope concentration area form a channel area, and form a source area and a drain area including the high concentration area and at least another portion of the slope concentration area. In the slope concentration area, the semiconductor layer satisfies an equation.
    Type: Application
    Filed: December 18, 2023
    Publication date: December 12, 2024
    Applicant: Samsung Display Co., LTD.
    Inventors: Tetsuhiro TANAKA, Yeon Keon MOON, Seok Hwan BANG
  • Patent number: 12148835
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: November 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe, Yuhei Sato, Yasumasa Yamane, Daisuke Matsubayashi
  • Patent number: 12108635
    Abstract: A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: October 1, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Jung Yub Seo, Ki Seong Seo, Yeong Gyu Kim, Hee Won Yoon
  • Publication number: 20240312998
    Abstract: A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 19, 2024
    Inventors: Jung Yub SEO, Tetsuhiro TANAKA, Hee Won YOON, Shin Beom CHOI
  • Patent number: 12046683
    Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: July 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Akihisa Shimomura, Naoto Yamade, Tomoya Takeshita, Tetsuhiro Tanaka
  • Patent number: 12027527
    Abstract: A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: July 2, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung Yub Seo, Tetsuhiro Tanaka, Hee Won Yoon, Shin Beom Choi
  • Publication number: 20240128380
    Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 18, 2024
    Inventors: Yutaka OKAZAKI, Akihisa SHIMOMURA, Naoto YAMADE, Tomoya TAKESHITA, Tetsuhiro TANAKA
  • Publication number: 20240105713
    Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 28, 2024
    Inventors: Tetsuhiro TANAKA, Yutaka OKAZAKI
  • Publication number: 20240090279
    Abstract: A display panel includes a first organic film layer, a first barrier layer disposed on first organic film layer, a shielding pattern disposed on the first barrier layer, a second barrier layer covering the shielding pattern and disposed on first barrier layer, a first active pattern disposed on the second barrier layer and overlapping the shielding pattern in a plan view, a gate electrode disposed on the first active pattern, an emission control line disposed on the first active pattern and adjacent to a first side of the gate electrode in the plan view, an upper compensation control line disposed on the emission control line and adjacent to a second side of gate electrode in the plan view, and a second active pattern disposed on the emission control line.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: YOON-JONG CHO, TETSUHIRO TANAKA, YOUNG-IN HWANG
  • Patent number: 11856826
    Abstract: A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 26, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Yeong-Gyu Kim, Kiseong Seo, Jonghyun Yun, Seunghyun Lee
  • Patent number: 11856823
    Abstract: A display panel includes a first organic film layer, a first barrier layer disposed on first organic film layer, a shielding pattern disposed on the first barrier layer, a second barrier layer covering the shielding pattern and disposed on first barrier layer, a first active pattern disposed on the second barrier layer and overlapping the shielding pattern in a plan view, a gate electrode disposed on the first active pattern, an emission control line disposed on the first active pattern and adjacent to a first side of the gate electrode in the plan view, an upper compensation control line disposed on the emission control line and adjacent to a second side of gate electrode in the plan view, and a second active pattern disposed on the emission control line.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoon-Jong Cho, Tetsuhiro Tanaka, Young-In Hwang