Patents by Inventor Tetsuhiro Tanaka

Tetsuhiro Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230071179
    Abstract: A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer ; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.
    Type: Application
    Filed: October 27, 2022
    Publication date: March 9, 2023
    Inventors: JUNG YUB SEO, Tetsuhiro Tanaka, Hee Won Yoon, Shin Beom Choi
  • Patent number: 11502110
    Abstract: A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung Yub Seo, Tetsuhiro Tanaka, Hee Won Yoon, Shin Beom Choi
  • Publication number: 20220352387
    Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
    Type: Application
    Filed: July 11, 2022
    Publication date: November 3, 2022
    Inventors: Yutaka OKAZAKI, Akihisa SHIMOMURA, Naoto YAMADE, Tomoya TAKESHITA, Tetsuhiro TANAKA
  • Publication number: 20220302314
    Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Hiromichi GODO, Tetsuhiro TANAKA
  • Patent number: 11404585
    Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: August 2, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Tetsuhiro Tanaka, Toshihiko Takeuchi, Yasumasa Yamane, Takayuki Inoue, Shunpei Yamazaki
  • Patent number: 11393930
    Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 19, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Akihisa Shimomura, Naoto Yamade, Tomoya Takeshita, Tetsuhiro Tanaka
  • Publication number: 20220020839
    Abstract: A display device includes a first active pattern disposed on a substrate, a first gate electrode disposed on the first active pattern, a second active pattern disposed on the first gate electrode, being electrically connected to the first gate electrode, and including an extension part extending in a first direction and a protrusion part protruding from the extension part in a second direction crossing the first direction, and a voltage line disposed on the second active pattern, extending in the first direction, and overlapping the protrusion part in an overlapping region. The voltage line contacts the protrusion part through a first contact, and the first contact entirely overlaps the overlapping region on a plane.
    Type: Application
    Filed: March 23, 2021
    Publication date: January 20, 2022
    Inventors: Seung-Hwan Cho, Wonsuk Choi, Tetsuhiro Tanaka, Jiryun Park, Seokje Seong, Seungwoo Sung, Jiseon Lee
  • Publication number: 20220005901
    Abstract: A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89.
    Type: Application
    Filed: June 15, 2021
    Publication date: January 6, 2022
    Inventors: Tetsuhiro TANAKA, Jung Yub SEO, Ki Seong SEO, Yeong Gyu KIM, Hee Won YOON
  • Patent number: 11217668
    Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 4, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Kazuki Tanemura, Daisuke Matsubayashi
  • Patent number: 11211407
    Abstract: A display device includes a polycrystalline semiconductor including a channel, a first electrode, and a second electrode of a driving transistor, a first gate insulating layer, a gate electrode of a driving transistor, a first electrode of a boost capacitor, a second gate insulating layer, a first interlayer insulating layer, an oxide semiconductor including a channel, a first electrode, and a second electrode of a second transistor, a channel, a first electrode, and a second electrode of a third transistor, and a second electrode of a boost capacitor, a third gate insulating layer disposed on the oxide semiconductor, a gate electrode of the second transistor overlapping the channel of the second transistor, a gate electrode of the third transistor overlapping the channel of the third transistor, and a second interlayer insulating layer disposed on the gate electrode of the second transistor and the gate electrode of the third transistor.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tetsuhiro Tanaka, Yeong-Gyu Kim, Ki Seong Seo, Seung Hyun Lee, Chang Ho Yi
  • Publication number: 20210384282
    Abstract: A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.
    Type: Application
    Filed: June 2, 2021
    Publication date: December 9, 2021
    Inventors: TETSUHIRO TANAKA, YEONG-GYU KIM, KISEONG SEO, JONGHYUN YUN, SEUNGHYUN LEE
  • Publication number: 20210359067
    Abstract: A display panel includes a first organic film layer, a first barrier layer disposed on first organic film layer, a shielding pattern disposed on the first barrier layer, a second barrier layer covering the shielding pattern and disposed on first barrier layer, a first active pattern disposed on the second barrier layer and overlapping the shielding pattern in a plan view, a gate electrode disposed on the first active pattern, an emission control line disposed on the first active pattern and adjacent to a first side of the gate electrode in the plan view, an upper compensation control line disposed on the emission control line and adjacent to a second side of gate electrode in the plan view, and a second active pattern disposed on the emission control line.
    Type: Application
    Filed: March 16, 2021
    Publication date: November 18, 2021
    Inventors: Yoon-Jong CHO, Tetsuhiro TANAKA, Young-In HWANG
  • Publication number: 20210320212
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Tetsuhiro TANAKA, Hirokazu WATANABE, Yuhei SATO, Yasumasa YAMANE, Daisuke MATSUBAYASHI
  • Patent number: 11133402
    Abstract: To provide a semiconductor device including an oxide semiconductor layer with high and stable electrical characteristics, the semiconductor device is manufactured by forming a first insulating layer, forming oxide over the first insulating layer and then removing the oxide n times (n is a natural number), forming an oxide semiconductor layer over the first insulating layer, forming a second insulating layer over the oxide semiconductor layer, and forming a conductive layer over the second insulating layer. Alternatively, the semiconductor device is manufactured by forming the oxide semiconductor layer over the first insulating layer, forming the second insulating layer over the oxide semiconductor layer, forming the oxide over the second insulating layer and then removing the oxide n times (n is a natural number), and forming the conductive layer over the second insulating layer.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 28, 2021
    Inventors: Tetsuhiro Tanaka, Ryo Tokumaru, Yasumasa Yamane, Akihisa Shimomura, Naoki Okuno
  • Publication number: 20210296367
    Abstract: A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.
    Type: Application
    Filed: October 26, 2020
    Publication date: September 23, 2021
    Inventors: Jung Yub SEO, Tetsuhiro TANAKA, Hee Won YOON, Shin Beom CHOI
  • Publication number: 20210257426
    Abstract: A display device includes a first thin film transistor disposed on a substrate. A first insulating interlayer covers lire first thin film transistor. An active pattern is disposed on the first insulating interlayer. The active pattern includes indium-gallium-zinc oxide (IGZO) having a thickness in a range of about 150 ? to about 400 ?. A gate insulation layer covers the active pattern A gate pattern is disposed on the gate insulation layer. A second insulating interlayer covers the gate pattern.
    Type: Application
    Filed: January 28, 2021
    Publication date: August 19, 2021
    Inventors: Tetsuhiro TANAKA, Yeong-Gyu KIM, Tae Sik KIM, Hee Yeon KIM, Ki Seong SEO, Seung Hyun LEE, Kyeong Woo JANG, Sug Woo JUNG
  • Publication number: 20210242199
    Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.
    Type: Application
    Filed: March 30, 2021
    Publication date: August 5, 2021
    Inventors: Tetsuhiro TANAKA, Yutaka OKAZAKI
  • Publication number: 20210210518
    Abstract: A display device includes a polycrystalline semiconductor including a channel, a first electrode, and a second electrode of a driving transistor, a first gate insulating layer, a gate electrode of a driving transistor, a first electrode of a boost capacitor, a second gate insulating layer, a first interlayer insulating layer, an oxide semiconductor including a channel, a first electrode, and a second electrode of a second transistor, a channel, a first electrode, and a second electrode of a third transistor, and a second electrode of a boost capacitor, a third gate insulating layer disposed on the oxide semiconductor, a gate electrode of the second transistor overlapping the channel of the second transistor, a gate electrode of the third transistor overlapping the channel of the third transistor, and a second interlayer insulating layer disposed on the gate electrode of the second transistor and the gate electrode of the third transistor.
    Type: Application
    Filed: August 6, 2020
    Publication date: July 8, 2021
    Applicant: Samsung Display Co., LTD.
    Inventors: Tetsuhiro TANAKA, Yeong-Gyu KIM, Ki Seong SEO, Seung Hyun LEE, Chang Ho YI
  • Patent number: 11049974
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 29, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe, Yuhei Sato, Yasumasa Yamane, Daisuke Matsubayashi
  • Publication number: 20210184042
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 17, 2021
    Inventors: Tetsuhiro TANAKA, Mitsuhiro ICHIJO, Toshiya ENDO, Akihisa SHIMOMURA, Yuji EGI, Sachiaki TEZUKA, Shunpei YAMAZAKI