Abstract: In semiconductor devices with nonvolatile memory modules embedded therein, a technology is provided which facilitates evaluation of the nonvolatile memory characteristics. An MCU includes a CPU, a flash memory, and an FPCC that controls write or erase operations to the flash memory. The FPCC executes a program used to perform write or other operations to the flash memory, thereby performing write or other operations to the flash memory in accordance with a command issued by the CPU. In the MCU, the FCU is configured to execute test firmware to evaluate the flash memory. In addition, a RAM can be used by both the CPU and FCU.

Abstract: In semiconductor devices with nonvolatile memory modules embedded therein, a technology is provided which facilitates evaluation of the nonvolatile memory characteristics. An MCU includes a CPU, a flash memory, and an FPCC that controls write or erase operations to the flash memory. The FPCC executes a program used to perform write or other operations to the flash memory, thereby performing write or other operations to the flash memory in accordance with a command issued by the CPU. In the MCU, the FCU is configured to execute test firmware to evaluate the flash memory. In addition, a RAM can be used by both the CPU and FCU.

Abstract: In semiconductor devices with nonvolatile memory modules embedded therein, a technology is provided which facilitates evaluation of the nonvolatile memory characteristics. An MCU includes a CPU, a flash memory, and an FPCC that controls write or erase operations to the flash memory. The FPCC executes a program used to perform write or other operations to the flash memory, thereby performing write or other operations to the flash memory in accordance with a command issued by the CPU. In the MCU, the FCU is configured to execute test firmware to evaluate the flash memory. In addition, a RAM can be used by both the CPU and FCU.

Abstract: A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.

Abstract: Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.

Abstract: The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.

Abstract: A row address decoder of a semiconductor memory device generates internal row address signals RAD<0:11> and /RAD<0:11> by switching most significant bit and least significant bit of row address signals RA<0:11> and /RA<0:11> that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD<0> and /RAD<0> of the internal row address signals corresponding to the most significant bits RA<11> and /RA<11> of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

Abstract: A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.

Abstract: The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.

Abstract: Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.

Abstract: A row address decoder of a semiconductor memory device generates internal row address signals RAD<0:11>and /RAD<0:11>by switching most significant bit and least significant bit of row address signals RA<0:11>and /RA<0:11>that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD<0>and /RAD<0>of the internal row address signals corresponding to the most significant bits RA<11>and /RA<11>of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent wold lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

Abstract: A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.

Abstract: A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.

Abstract: A data demultiplexer in a media demultiplexer dissolves a bit stream into video packets and audio packets. A CRC calculating unit subjects data from a CRC character isolating unit to the same calculation as performed at the encoding end and outputs a result of calculation to an error information adding unit. The error information adding unit compares the result of calculation with a CRC character attached to the video packet so as to determine whether they match. The error information adding unit adds error information based on a result of determination to the video packet. The resultant revised video packet is output to a video decoder via a buffer.

Abstract: A word line drive signal generating circuit, which generates a word line drive signal RX to a selected word line, includes an RX generating circuit responsive to an external row address strobe signal *RAS (or/RAS) for generating word line drive signal RX, a determination circuit responsive to an operating power supply voltage level or an externally applied signal for determining whether the word line drive signal RX should be boosted up, and a boosting circuit responsive to the word line drive signal RX and an output of determination circuit for boosting up the word line drive signal RX. The word line drive signal RX is boosted up to or above the operating power supply voltage level only when the determination circuit determines it to be necessary. Thereby, a high voltage is not normally applied to the word line, so that deterioration of breakdown voltage of the word line is prevented, and the reliability of the word line is improved.

Abstract: A dynamic random access memory comprises memory cells (MA1-Man) and sense amplifies (SA1-SAn) in a memory array region III and memory cells (MB1-MBn) and sense amplifies (SB1-SBn) in a memory array region IV. In reading operation, first, the sense amplifiers in one region comprising a memory cell designated by an address signal are activated and then sense amplifiers in the other region are activated. As a result, since amplifying operation by the sense amplifiers is performed sequentially, a peak value of a current consumed by the amplification can be reduced.