Patents by Inventor Tetsuji Gotoh

Tetsuji Gotoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit for holding an output signal of an output terminal in a non-operating state
    Patent number: 6727743
    Abstract: In a static circuit or the like, upper and lower terminals are both set to a first power supply potential Vdd1 in the operating state of an inverter circuit. In the non-operating state, the power supply potential of the upper terminal is reduced to a second power supply potential Vdd2 (<<Vdd1). Provided that an input signal of the inverter circuit has a potential Vdd2 (H level), an output signal thereof must be held at the ground potential (L level) in the operating state. This requires that a conductance Gp of a PMOS transistor and a conductance Gn of a NMOS transistor satisfy the relation: Gp<Gn. Therefore, a well terminal (lower terminal) of the PMOS transistor is set to a potential higher than the power supply potential Vdd2 in order to maintain the relation: Gp<Gn. Accordingly, a signal determined by the circuit in the operating state can be held even in the non-operating state, and the power supply voltage is set to an extremely low potential in the non-operating state of the circuit.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: April 27, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiichi Kusumoto, Tomoyuki Kumamaru, Takashi Andoh, Tetsuji Gotoh
  • Semiconductor integrated circuit
    Publication number: 20030025552
    Abstract: In a static circuit or the like, upper and lower terminals are both set to a first power supply potential Vdd1 in the operating state of an inverter circuit. In the non-operating state, the power supply potential of the upper terminal is reduced to a second power supply potential Vdd2 (<<Vdd1). Provided that an input signal of the inverter circuit has a potential Vdd2 (H level), an output signal thereof must be held at the ground potential (L level) in the operating state. This requires that a conductance Gp of a PMOS transistor and a conductance Gn of a NMOS transistor satisfy the relation: Gp<Gn. Therefore, a well terminal (lower terminal) of the PMOS transistor is set to a potential higher than the power supply potential Vdd2 in order to maintain the relation: Gp<Gn. Accordingly, a signal determined by the circuit in the operating state can be held even in the non-operating state, and the power supply voltage is set to an extremely low potential in the non-operating state of the circuit.
    Type: Application
    Filed: July 15, 2002
    Publication date: February 6, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiichi Kusumoto, Tomoyuki Kumamaru, Takashi Andoh, Tetsuji Gotoh