Patents by Inventor Tetsuji Maruyama

Tetsuji Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10720917
    Abstract: A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: July 21, 2020
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Tetsuji Maruyama
  • Publication number: 20180123582
    Abstract: A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.
    Type: Application
    Filed: October 25, 2017
    Publication date: May 3, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Tetsuji Maruyama
  • Patent number: 8405459
    Abstract: A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: March 26, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Tetsuji Maruyama
  • Publication number: 20110291760
    Abstract: A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages.
    Type: Application
    Filed: April 27, 2011
    Publication date: December 1, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuji Maruyama