Abstract: Disclosed herein is an apparatus that includes a plurality of signal wiring patterns, a plurality of shield patterns each provided between corresponding two of the signal wiring patterns, a common pattern coupled to each of the plurality of shield patterns, and a transistor coupled between the common pattern and a power line supplied with a fixed power potential.

Abstract: Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.

Abstract: A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge.

Abstract: Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal.

Abstract: Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.

Abstract: A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge.

Abstract: A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge.

Abstract: A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge.

Abstract: For reducing the area for read/write bus lines to a half and shortening the length of the read/write bus lines so as to speed up the operation, the locating positions of input/output circuits for the corresponding bits, of memory blocks MB1 and MB3a located to oppose to each other and to interpose therebetween an active circuit area ACA and of memory blocks MB2a and MB4 located to oppose to each other and to interpose therebetween the active circuit area ACA, are made different from each other. Read/write bus lines RWB1 to RWB4 of the same length are formed and located to interconnect between the inputs/outputs for the corresponding bits, of the opposing memory blocks, by traversing an empty region between circuit blocks CB in the active circuit area ACA, and in such a manner that each two read/write bus lines extend between the memory blocks MB1 and MB2a and between the memory blocks MB3a and MB4.

Abstract: An image data output apparatus including a page-link memory, for storing data pertaining to the relationship between the logical address and the physical address, of the image data, and an address-translation unit for translating logical page addresses into physical page addresses. The apparatus can perform quick, accurate accessing of the image data, in a direction across the adjacent pages. The frame memory can undergo reallocation, so that the least possible data is transferred upon generation of the boundary condition of a frame memory.