Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

Abstract: A method of manufacturing a semiconductor storage device according to an embodiment of the present invention includes forming dummy cells 611, to 618 at a position adjacent to a reference cell 412, and implanting an impurity into the dummy cells 611, to 618 using a mask that covers the reference cell 412. Here, the process of implanting the impurity is carried out so that the impurity exudes out of the dummy cells 611, to 618 to the reference cell 412.

Abstract: A method of manufacturing a semiconductor storage device according to an embodiment of the present invention includes forming dummy cells 611, to 618 at a position adjacent to a reference cell 412, and implanting an impurity into the dummy cells 611, to 618 using a mask that covers the reference cell 412. Here, the process of implanting the impurity is carried out so that the impurity exudes out of the dummy cells 611, to 618 to the reference cell 412.

Abstract: A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Abstract: A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Abstract: According to one embodiment, a multistage readout circuit may include a smaller circuit size and/or faster circuit response. A memory cell (002) may have more than two states (VT0-VT3). Determination of a particular state can involve various stage results generated by activating a word line at different levels. A sense amplifier (003) can provide an output value at each stage. In one arrangement, a second stage value can determine if a memory cell (002) has two of four states and can be latched in a first latch circuit (041). Such a second stage value can then determine if a first stage value or third stage value is latched in a second latch circuit (042). A first/third value can determine if a memory cell (002) has one of the two states initially determined by the second stage value.

Abstract: In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed.

Abstract: In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed.

Abstract: A pulse generating circuit which has a first and a second delay circuit selectively operable as a delay circuit or a resetting circuit. The delay circuits each has a discharge transistor and a charge transistor in order to fix the potential on its associated node rapidly when operating as a resetting circuit. Even when short pulses are continuously input as an input signal by accident, the circuitry surely outputs a single pulse transitioning at the same time as the first change in the input signal and having a desired duration since the last change in the input signal.