Patents by Inventor Tetsuji Yamaguchi
Tetsuji Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7652321Abstract: In a process of manufacturing elements of different structures and characteristics on the same substrate at the same time, the number of steps is increased and complicated. In view of this, the invention provides a semiconductor device and a manufacturing process thereof in which elements of different structures are formed on the same substrate while reducing the number of steps. According to the invention, in accordance with a memory transistor that requires the largest number of steps when being formed among elements that forms a semiconductor memory device, other high speed transistor and high voltage transistor are efficiently manufactured. Thus, the number of steps is suppressed and a low cost semiconductor memory device can be manufactured.Type: GrantFiled: March 7, 2005Date of Patent: January 26, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuji Yamaguchi, Kiyoshi Kato
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Publication number: 20090290195Abstract: An image forming system including a management device, an image forming apparatus including an auxiliary storage device, and a plurality of information processing devices, which are coupled to one another via a network, the image forming system being configured as follows. The management device is designed to: acquire a box information file regarding a document box created on the auxiliary storage device from the image forming apparatus via the network; and transmit the box information file to each of the plurality of information processing devices in its original format and a state after conversion thereof into a predetermined format. The plurality of information processing devices each control a printer driver compatible with the image forming apparatus to read the received box information file.Type: ApplicationFiled: February 19, 2009Publication date: November 26, 2009Applicant: KYOCERA MITA CORPORATIONInventors: Tetsuji Yamaguchi, Daisuke Yoshida
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Patent number: 7608492Abstract: It is an object of the present invention to apply a technique for removing the adverse effect of a substrate shrinkage due to a heat treatment, and further forming a fine and high-quality insulating film, and a semiconductor device that can realize high-performance and high-reliability by using the same, to a transistor formed by laminating a semiconductor film or an insulating film over a glass substrate. A heat treatment that is necessary in a step of forming a thin film element by laminating a semiconductor film or an insulating film over a glass substrate is performed without thermally-damaging the substrate. For the purpose, a light-absorbing layer that can absorb pulsed light over a particular portion of the substrate in which the thin film element is formed is locally formed, and the heat treatment is performed.Type: GrantFiled: January 14, 2008Date of Patent: October 27, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Shunpei Yamazaki, Tetsuji Yamaguchi
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Patent number: 7605023Abstract: To apply a technique of forming a dense insulating film with a high quality in a thin film element such as a TFT formed on a glass substrate by eliminating an influence of contraction of the substrate caused by heat treatment in a manufacturing process for the element, and a semiconductor device using the same, which enables high performance and reliability. In a step of forming the thin film element composed of a laminate of plural thin films using the glass substrate, in order to avoid a thermal damage on the substrate, heat treatment is performed such that a coating film for absorbing radiation from a heat source is locally formed in a specific portion of the substrate where the thin film element is to be formed. For the substrate to be applied in the present invention, a raw material low in absorptance with respect to the radiation from the heat source and hard to be heated is adopted.Type: GrantFiled: August 28, 2003Date of Patent: October 20, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Shunpei Yamazaki, Tetsuji Yamaguchi
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Publication number: 20090256226Abstract: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.Type: ApplicationFiled: April 8, 2009Publication date: October 15, 2009Applicant: Sony CorporationInventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
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Patent number: 7575993Abstract: To provide a method of forming a wiring for the purpose of providing a semiconductor device, which is superior in reliability and cost performance. Further, to provide methods of manufacturing a semiconductor device and a display device by using the method of forming the wiring according to the present invention. According to the present invention, when a wiring material and the like is directly patterned on a substrate mainly having an insulating surface by droplet discharging method, a wiring is formed at a position including at least an opening in contact with an underlying portion on an insulating film provided with the opening by dropping a liquid droplet containing a conductive composition by droplet discharging method. By heating the substrate with the wiring formed thereon, a surface of the wiring on the opening and a surface of the wiring other than the wiring on the opening are approximately leveled, and the opening is filled.Type: GrantFiled: March 16, 2007Date of Patent: August 18, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Tetsuji Yamaguchi
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Publication number: 20090195154Abstract: It is an object of the present invention to provide a reliable display device and a method for manufacturing the display device reducing the number of manufacturing steps, and with higher yield. A display device according to the invention includes a plurality of display elements each having a first electrode, a layer containing an organic compound, and a second electrode. The display device further includes a heat-resistant planarizing film over a substrate having an insulating surface, a first electrode over the heat-resistant planarizing film, a wiring covering an end portion of the first electrode, a partition wall covering the end portion of first electrode and the wiring, a layer containing an organic compound, and a second electrode over the layer containing an organic compound.Type: ApplicationFiled: March 18, 2009Publication date: August 6, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Masaharu NAGAI, Yutaka MATSUDA, Kengo AKIMOTO, Gen FUJII, Tetsuji YAMAGUCHI
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Publication number: 20090194803Abstract: The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption semiconductor device and a manufacturing method of the semiconductor device. According to one aspect of the present invention, a semiconductor device that has a semiconductor nonvolatile memory element transistor over an insulating surface in which a floating gate electrode of the memory transistor is formed by a plurality of conductive particles or semiconductor particles is provided.Type: ApplicationFiled: January 29, 2009Publication date: August 6, 2009Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Tetsuji Yamaguchi, Hiromichi Godo
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Publication number: 20090189235Abstract: A solid-state imaging device having a light-receiving section that photoelectrically converts incident light includes an insulating film formed on a light-receiving surface of the light-receiving section and a film and having negative fixed charges formed on the insulating film. A hole accumulation layer is formed on a light-receiving surface side of the light-receiving section. A peripheral circuit section in which peripheral circuits are formed is provided on a side of the light-receiving section. The insulating film is formed between a surface of the peripheral circuit section and the film having negative fixed charges such that a distance from the surface of the peripheral circuit section to the film having negative fixed charges is larger than a distance from a surface of the light-receiving section to the film having negative fixed charges.Type: ApplicationFiled: December 19, 2008Publication date: July 30, 2009Applicant: SONY CORPORATIONInventors: Harumi Ikeda, Susumu Hiyama, Takashi Ando, Kiyotaka Tabuchi, Tetsuji Yamaguchi, Yuko Ohgishi
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Patent number: 7524709Abstract: A technology for easily forming a multi-layer wiring structure that is fine and reliable. In the multi-layer wiring structure, the lower-layer wiring and the upper-layer wiring that are formed to sandwich an insulating layer are electrically connected to each other in a projection formed in the lower-layer wiring. The projection includes a columnar conductive member and the upper and lower layers thereof and each of the lower layer and the upper layer is formed of a conductive layer formed over the entire lower-layer wiring. The upper-layer is electrically connected to the lower-layer wiring in the portion where the projection is exposed substantially on the same plane as the top surface of the insulating layer.Type: GrantFiled: January 29, 2007Date of Patent: April 28, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akira Ishikawa, Tetsuji Yamaguchi
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Patent number: 7520790Abstract: It is an object of the present invention to provide a reliable display device and a method for manufacturing the display device reducing the number of manufacturing steps, and with higher yield. A display device according to the invention includes a plurality of display elements each having a first electrode, a layer containing an organic compound, and a second electrode. The display device further includes a heat-resistant planarizing film over a substrate having an insulating surface, a first electrode over the heat-resistant planarizing film, a wiring covering an end portion of the first electrode, a partition wall covering the end portion of first electrode and the wiring, a layer containing an organic compound, and a second electrode over the layer containing an organic compound.Type: GrantFiled: September 14, 2004Date of Patent: April 21, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masayuki Sakakura, Masaharu Nagai, Yutaka Matsuda, Kengo Akimoto, Gen Fujii, Tetsuji Yamaguchi
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Patent number: 7521368Abstract: The present invention provides a method for manufacturing a semiconductor device having high characteristic and reliability. The etching damage during dry etching after forming an electrode or a wiring over an insulating film is prevented. The damage is suppressed by forming a conductive layer so that charged particles due to plasma during dry etching are not generated in a semiconductor layer. Accordingly, it is an object of the invention to provide a method not for generating the deterioration of the transistor characteristic especially in a thin film transistor having a minute structure.Type: GrantFiled: May 4, 2005Date of Patent: April 21, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuji Yamaguchi, Etsuko Asano, Naomi Yazaki, Tomoya Futamura, Tomoko Nishikawa
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Publication number: 20090096049Abstract: A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section.Type: ApplicationFiled: October 3, 2008Publication date: April 16, 2009Applicant: SONY CORPORATIONInventors: Itaru Oshiyama, Takashi Ando, Susumu Hiyama, Tetsuji Yamaguchi, Yuko Ohgishi, Harumi Ikeda
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Publication number: 20090091756Abstract: In order to improve an accuracy of an autocorrelation function, a correlator comprises a counter 61 for receiving a pulse signal at given time intervals (sampling times) and counting the number of pulses; a shift register 63 for receiving the number of pulses counted by the counter 61 and performing sequential time delay; an operation part 64 for performing a product-sum operation of an output from the counter 61 and that delayed by the shift register 63 for each channel; and a control part 65 for setting a delay time or a sampling time by the shift register 63 on a basis of a relationship of the Fibonacci sequence.Type: ApplicationFiled: October 6, 2008Publication date: April 9, 2009Applicant: HORIBA, Ltd.Inventors: Tetsuji YAMAGUCHI, Shigeyuki KAWARABAYASHI
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Patent number: 7504663Abstract: The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption semiconductor device and a manufacturing method of the semiconductor device. According to one aspect of the present invention, a semiconductor device that has a semiconductor nonvolatile memory element transistor over an insulating surface in which a floating gate electrode of the memory transistor is formed by a plurality of conductive particles or semiconductor particles is provided.Type: GrantFiled: May 25, 2005Date of Patent: March 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Tetsuji Yamaguchi, Hiromichi Godo
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Patent number: 7504327Abstract: In the invention, a low concentration impurity region is formed between a channel formation region and a source region or a drain region in a semiconductor layer and covered with a gate electrode layer in a thin film transistor The semiconductor layer is doped obliquely to the surface thereof using the gate electrode layer as a mask to form the low concentration impurity region. The semiconductor layer is formed to have an impurity region including an impurity element for imparting one conductivity which is different from conductivity of the thin film transistor, thereby being able to minutely control the properties of the thin film transistor.Type: GrantFiled: June 9, 2005Date of Patent: March 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Tetsuji Yamaguchi, Hiromichi Godo
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Publication number: 20080211024Abstract: An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.Type: ApplicationFiled: May 31, 2005Publication date: September 4, 2008Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Tetsuji Yamaguchi, Etsuko Asano, Konami Izumi
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Publication number: 20080191279Abstract: An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode.Type: ApplicationFiled: April 4, 2008Publication date: August 14, 2008Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuji Yamaguchi, Kengo Akimoto, Hiroki Kayoiji, Toru Takayama
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Publication number: 20080179599Abstract: A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a sidewall is formed over the base insulating film, and a metal film is formed to cover the TFT. Annealing is conducted by RTA or the like at such a temperature that does not cause shrinkage of the substrate, and a high-resistant metal silicide layer is formed in source and drain regions. After removing an unreacted metal film, laser irradiation is conducted for the second annealing; therefore a silicide reaction proceeds and the high-resistant metal silicide layer becomes a low-resistant metal silicide layer.Type: ApplicationFiled: October 22, 2007Publication date: July 31, 2008Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuji YAMAGUCHI, Atsuo Isobe, Satoru Saito
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Publication number: 20080166138Abstract: Disclosed is an image forming system, which comprises an image forming apparatus, and a toner container mountable to the image forming apparatus. The image forming apparatus includes a control section, and an information acquisition section which acquires the toner-quality information about a toner container which is demountably mounted thereto. The control section is operable, based on the toner-quality information acquired by the information acquisition section, to identify the quality of the toner contained in the toner container and set a printing function based on the identified toner quality.Type: ApplicationFiled: January 4, 2008Publication date: July 10, 2008Applicant: Kyocera Mita CorporationInventors: Hiroyuki Hanano, Toru Yasui, Tetsuji Yamaguchi