Patents by Inventor Tetsuma Sakurai

Tetsuma Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5732394
    Abstract: In a word speech recognition method which performs pattern matching between unknown speech pattern and multiple reference templates and detects that one of the reference templates which provides the smallest one of distance measures detected between the unknown speech pattern and the reference templates, when the difference d between the speech period length of the unknown speech pattern and the speech period length of a selected reference template exceeds a fixed threshold value .epsilon..sub.1, partial patterns are extracted from the unknown speech pattern, each starting at a different position, and the minimum one of the distances obtained by pattern matching between these extracted partial patterns and the selected reference template is determined to be the distance between the selected reference template and the unknown speech pattern. When the difference d is in the range of -.epsilon..sub.2 .ltoreq.d.ltoreq..epsilon..sub.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: March 24, 1998
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yoshio Nakadai, Tetsuma Sakurai, Yutaka Nishino
  • Patent number: 5442561
    Abstract: Production schedules are executed for production machines and lots having high importance or priority from among lots being objects of production process by the production machines, and progress of production process is managed by a scheduler based on the production schedules. For those lots whose progresses are delayed, the production schedules are automatically adjusted by the scheduler so that the delays can be eliminated.
    Type: Grant
    Filed: May 10, 1993
    Date of Patent: August 15, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masahiro Yoshizawa, Tetsuma Sakurai
  • Patent number: 4419685
    Abstract: A lateral transistor having a high breakdown voltage and operable with an improved current amplification factor and an improved cut-off frequency comprises in a semiconductor substrate of one conductivity type, a base layer of the one conductivity type and an emitter layer of the other conductivity type formed in the base layer. A first collector layer of the other conductivity type is formed in the one principal surface of the substrate apart from the base layer and a second collector layer of the same conductivity type having an impurity concentration lower than that of the first collector layer is formed between the first collector layer and the base layer in contact with the latter layers. Emitter, base and collector electrodes make ohmic contact with the emitter, base and first collector layers respectively. The emitter electrode extends on a passivation film covering the one principal surface of the substrate to terminate at a point on the second collector layer.
    Type: Grant
    Filed: March 19, 1981
    Date of Patent: December 6, 1983
    Assignees: Hitachi, Ltd., Nippon Telegraph & Telephone Public Corporation
    Inventors: Yoshitaka Sugawara, Tatsuya Kamei, Tetsuma Sakurai
  • Patent number: 4408386
    Abstract: Spaced recesses are formed in a surface of a low impurity concentration P type single-crystal substrate by using a mask. A P type impurity is diffused at a high concentration into an entire surface of the substrate including the recesses to form a P type diffused layer, and an N type layer is epitaxially grown on the P type diffused layer. Then, mask layers are formed on bottom surfaces of the recesses in the epitaxially grown N type layer and this N type layer is anisotropically etched by using the mask layers to form island regions in the recesses. After removing the mask layers, N type diffused layers are formed to cover the island regions. An insulating film (SiO.sub.2) acting to isolate completed transistor elements is formed on the P and N type diffused layers, and a polycrystalline silicon layer acting as a support of a dielectrically isolated integrated circuit device is formed on the insulating film.
    Type: Grant
    Filed: December 2, 1981
    Date of Patent: October 11, 1983
    Assignees: Oki Electric Industry Co., Ltd., Nippon Telegraph and Telephone Public Corporation
    Inventors: Tetsuya Takayashiki, Taiji Usui, Tetsuma Sakurai
  • Patent number: 4393573
    Abstract: The semiconductor device is provided with semiconductor elements having the complementary characteristics and high breakdown strength. These semiconductor elements are formed in N and P islands respectively each having an inverted frustum shape.Surfaces of the frustum are inclined by an angle determined by semiconductor crystal structure. Side and bottom surfaces of the islands are formed adjacent to an insulating layer and both islands are supported part from the polycrystalline semiconductor layer. All side and bottom surfaces of the islands adjacent the insulating layer are made of high impurity substance of the same type as respective islands.
    Type: Grant
    Filed: August 26, 1980
    Date of Patent: July 19, 1983
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Kotaro Kato, Tetsuma Sakurai