Patents by Inventor Tetsunori Maeda

Tetsunori Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5841713
    Abstract: On carrying out a wafer test for a plurality of semiconductor wafers, N in number, each having a plurality of chips, an initial wafer test is carried out for all of the semiconductor wafers to produce an initial wafer test result representing that each chip of each of the semiconductor wafers is any one of a good chip, a defective chip, and a predictive good chip which is predicted as the good chip if subjected to trimming. Subsequently, each of the predictive good chips is subjected to the trimming to be repaired as the good chips. After that, a final wafer test (8001-8012) is carried out for a reduced number M (M being a positive integer less than N) of sampled wafers sampled among the semiconductor wafers to produce a final wafer test result representing that each chip of each of the sampled wafers is any one of the good chip and the defective chip.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: November 24, 1998
    Assignee: NEC Corporation
    Inventor: Tetsunori Maeda
  • Patent number: 5568408
    Abstract: An automatic repair data editing system is associated with a repairing system for rescuing defective semiconductor memories fabricated on semiconductor wafers from rejection. The system edits repair data that is partially duplicated due to a trouble in the repairing system, and allows the repairing system to automatically carry out a repair work on the defective semiconductor memories.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: October 22, 1996
    Assignee: NEC Corporation
    Inventor: Tetsunori Maeda