Patents by Inventor Tetsuo Fukada
Tetsuo Fukada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10293494Abstract: A bulk workpiece picking system is configured by including: a robot which is provided with an electromagnetic hand capable of magnetically attracting a metal workpiece; a determination section which determines whether or not the workpiece is magnetically attracted by the electromagnetic hand; and a magnetic force control section which controls the magnetic force of the electromagnetic hand, the magnetic force control section being configured such that: before it is determined by the determination section that the magnetic attraction is performed; the magnetic force control section sets a magnitude of the magnetic force of the electromagnetic hand so that the electromagnetic hand can suspend one workpiece and cannot suspend two workpieces; and then, after it is determined by the determination section that the magnetic attraction is performed, the magnetic force control section increases the magnetic force of the electromagnetic hand.Type: GrantFiled: February 14, 2017Date of Patent: May 21, 2019Assignee: FANUC CORPORATIONInventor: Tetsuo Fukada
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Publication number: 20170252929Abstract: A bulk workpiece picking system is configured by including: a robot which is provided with an electromagnetic hand capable of magnetically attracting a metal workpiece; a determination section which determines whether or not the workpiece is magnetically attracted by the electromagnetic hand; and a magnetic force control section which controls the magnetic force of the electromagnetic hand, the magnetic force control section being configured such that: before it is determined by the determination section that the magnetic attraction is performed; the magnetic force control section sets a magnitude of the magnetic force of the electromagnetic hand so that the electromagnetic hand can suspend one workpiece and cannot suspend two workpieces; and then, after it is determined by the determination section that the magnetic attraction is performed, the magnetic force control section increases the magnetic force of the electromagnetic hand.Type: ApplicationFiled: February 14, 2017Publication date: September 7, 2017Applicant: FANUC CORPORATIONInventor: Tetsuo FUKADA
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Publication number: 20050095091Abstract: An inexpensive manufacturing cell. The manufacturing cell includes a robot provided with a traveling shaft slider traveling along a traveling shaft device. A support conveying device is attached to the traveling shaft slider via a connecting arm. A plurality of supports are stocked in a support stocker. An engaging device is attached to a forward end portion of the robot arm. Pins of the engaging device are engaged in pin holes for engagement of the desired support accommodated in the support stocker. When the support is pushed or pulled, it is put on the support conveying device. In this state of engagement, the traveling shaft device is driven to move the robot. The support is positioned at a position of a manufacturing machine to which the support should be attached. When the robot is driven to push the support on the support conveying device, the support is pushed out onto a table of the manufacturing machine.Type: ApplicationFiled: October 14, 2004Publication date: May 5, 2005Applicant: FANUC LTDInventor: Tetsuo Fukada
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Publication number: 20030222349Abstract: A plurality of interconnection layers arranged at the same level are connected by an anti-diffusion insulating layer in a lateral direction. Interconnection layers arranged at different levels are electrically connected through a plug portion in a vertical direction. A second interlayer film is arranged only at a region directly below the interconnection layer and connects the interconnection layer with the anti-diffusion insulating layer in the vertical direction. A hollow space or an interlayer film with a low dielectric constant of at most 2.5 is located laterally adjacent to each of the plurality of interconnection layers. Thus, a semiconductor device having a multilayer interconnection structure that can improve both the strength of the interconnection layers and the transmission speed of signals, and a method of manufacturing the semiconductor device can be obtained.Type: ApplicationFiled: October 30, 2002Publication date: December 4, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shingo Tomohisa, Mutsumi Tsuda, Tetsuo Fukada, Masakazu Taki, Kenji Shintani
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Patent number: 6335570Abstract: A semiconductor device capable of preventing diffusion of a particle of copper or the like which forms a conductive layer is provided without any increase in the number of manufacturing the steps. Further, a semiconductor device preventing diffusion of a particle forming a conductive layer into an insulating layer even when a width of the conductive layer is increased is provided. The semiconductor device includes: an insulating layer 2; a barrier layer 4; a conductive layer 5; a barrier layer 6 having an opening 11; an insulating layer 7 having a through hole 8 exposing a surface of conductive layer 5 and a part of a surface of barrier layer 6; a barrier layer 9 formed on a surface of said through hole 8 and insulating layer 7 which is in contact with an upper surface 6a of barrier layer 6; and a conductive layer 10 filling opening 11 and through hole 8.Type: GrantFiled: April 20, 1999Date of Patent: January 1, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takeshi Mori, Yoshihiko Toyoda, Tetsuo Fukada, Yoshiyuki Kitazawa
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Publication number: 20010045652Abstract: A semiconductor device capable of preventing diffusion of a particle of copper or the like which forms a conductive layer is provided without any increase in the number of manufacturing the steps. Further, a semiconductor device preventing diffusion of a particle forming a conductive layer into an insulating layer even when a width of the conductive layer is increased is provided. The semiconductor device includes: an insulating layer 2; a barrier layer 4; a conductive layer 5; a barrier layer 6 having an opening 11; an insulating layer 7 having a through hole 8 exposing a surface of conductive layer 5 and a part of a surface of barrier layer 6; a barrier layer 9 formed on a surface of said through hole 8 and insulating layer 7 which is in contact with an upper surface 6a of barrier layer 6; and a conductive layer 10 filling opening 11 and through hole 8.Type: ApplicationFiled: April 20, 1999Publication date: November 29, 2001Inventors: TAKESHI MORI, YOSHIHIKO TOYODA, TETSUO FUKADA, YOSHIYUKI KITAZAWA
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Patent number: 6303495Abstract: Copper material is exposed on the surface of a TiN film (an underlying film) formed in the main surface of a silicon substrate with a silicon oxide film interposed. Subsequently, a thin copper film is formed on TiN film. Thus, the thin copper film can be formed on the film including metal with high melting point or nitride thereof with high adhesion by means of CVD.Type: GrantFiled: March 11, 1998Date of Patent: October 16, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takeshi Mori, Tetsuo Fukada, Makiko Hasegawa, Yoshihiko Toyoda
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Publication number: 20010019847Abstract: Copper material is exposed on the surface of a TiN film (an underlying film) formed in the main surface of a silicon substrate with a silicon oxide film interposed. Subsequently, a thin copper film is formed on TiN film. Thus, the thin copper film can be formed on the film including metal with high melting point or nitride thereof with high adhesion by means of CVD.Type: ApplicationFiled: March 11, 1998Publication date: September 6, 2001Inventors: TAKESHI MORI, TETSUO FUKADA, MAKIKO HASEGAWA, YOSHIHIKO TOYODA
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Patent number: 6215189Abstract: A highly reliable semiconductor device having a contact hole with a sufficient area can be obtained. An interlevel insulating film is formed on a conductive region having a first width. A through hole which exposes the conductive region is formed at the interlevel insulating film. A coating film is formed on the interlevel insulating film. In the coating film, an opening having a second width larger than the first width is formed in a region located on the through hole. An interconnect line is formed in a region located on the opening. A conductor film for electrically connecting the conductive region and the interconnect line is generated within the through hole.Type: GrantFiled: April 30, 1999Date of Patent: April 10, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshihiko Toyoda, Tetsuo Fukada, Takeshi Mori, Yoshiyuki Kitazawa
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Patent number: 6184124Abstract: A method of preparing a multilevel embedded wiring system for an IC comprising a first wiring formation step, a first connecting portion formation step, and a second wiring formation step, wherein the first wiring formation step comprises forming a first trench for a first embedded wiring in a first insulating layer disposed on a substrate and embedding in the first trench, in turn, a first conductive layer and a first conductive capping layer; the first connecting portion formation step comprises forming a second insulating layer on the first insulating layer and the first conductive capping layer, forming a via-hole in a part of the second insulating layer at the first conductive capping layer, and embedding a conductive connecting portion in the via-hole and connected to the first conductive layer; and the second formation step comprises forming a third insulating layer on the second insulating layer and the conductive connecting portion, forming a second trench for a second wiring in the third insulatingType: GrantFiled: May 14, 1998Date of Patent: February 6, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Makiko Hasegawa, Yoshihiko Toyoda, Takeshi Mori, Tetsuo Fukada
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Patent number: 6107687Abstract: A Cu interconnection layer is formed in a trench provided in an insulating layer with a base layer interposed therebetween, an adhesion layer is formed on the Cu interconnection layer and a cap layer is formed on the adhesion layer to restrict exfoliation of the cap layer formed on the Cu interconnection layer buried in the trench formed in the insulating layer.Type: GrantFiled: March 16, 1998Date of Patent: August 22, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Fukada, Takeshi Mori, Makiko Hasegawa, Yoshihiko Toyoda
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Patent number: 6039808Abstract: In a CVD apparatus for Cu formation using as a raw material, a mixture of a solvent and a liquid raw material including Cu(HFA) and adducted molecules or a solid raw material including Cu(HFA) and adducted molecules, a fluorinated organic polymer contained, a fluorinated metal, an insulator or a Ti compound is provided on a surface of a member at a portion where the raw material exists.Type: GrantFiled: March 17, 1998Date of Patent: March 21, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshihiko Toyoda, Tetsuo Fukada, Takeshi Mori, Makiko Hasegawa
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Patent number: 5892286Abstract: To form a plurality of patterned conductor leads in the same layer of an integrated circuit, an insulating film is etched to form a plurality of patterned grooves by plasma etching using an etching gas containing carbon and fluorine to which an additive gas containing carbon is added. The etching rate is substantially proportional to the groove width, so that the groove depth is substantially proportional to the groove width. Grooves are filled with a conductive material to form patterned conductor leads. Thus, an aspect ratio of the patterned conductor leads is kept in a certain range, resulting in an improvement in yield and reliability of the conductor leads. The conductor leads formed of material containing copper are coated with a diffusion preventive film.Type: GrantFiled: December 3, 1996Date of Patent: April 6, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshihiko Toyoda, Takeshi Mori, Tetsuo Fukada, Makiko Hasegawa
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Patent number: 5793112Abstract: The multilevel embedded wiring system for an IC has a capping layer on the conductive layer in channels or trenches in insulating layers. The capping layer prevents halation of light in a lithography process, resulting in a high precision structure. Even if Cu is used as the conductive material, the resulting wiring resistivity is still low and the diffusion and oxidation of Cu are prevented.Type: GrantFiled: September 18, 1996Date of Patent: August 11, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Makiko Hasegawa, Yoshihiko Toyoda, Takeshi Mori, Tetsuo Fukada