Patents by Inventor Tetsuo Hikawa
Tetsuo Hikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6677214Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: June 12, 2000Date of Patent: January 13, 2004Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6225668Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 25, 1997Date of Patent: May 1, 2001Assignees: Mega Chips Corporation, Silicon Technology CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6177706Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atoms currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anistropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 27, 1997Date of Patent: January 23, 2001Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6137120Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 27, 1997Date of Patent: October 24, 2000Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6106734Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diaphragm which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 25, 1997Date of Patent: August 22, 2000Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6025252Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 25, 1997Date of Patent: February 15, 2000Assignee: Mega Chips CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 5895887Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, power supply pins and ground pins are provided on opposite edges of a package with input address pins being arranged therebetween and output data pins being arranged outside the same. Control pins and a nonconnected excess pin are arranged in the center. This allows the package to omit wires and reduce chip size.Type: GrantFiled: July 21, 1997Date of Patent: April 20, 1999Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5866940Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.Type: GrantFiled: July 21, 1997Date of Patent: February 2, 1999Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5847449Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.Type: GrantFiled: July 21, 1997Date of Patent: December 8, 1998Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5825083Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.Type: GrantFiled: July 21, 1997Date of Patent: October 20, 1998Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5753553Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.Type: GrantFiled: February 28, 1996Date of Patent: May 19, 1998Assignee: Mega Chips CorporationInventors: Tetsuo Hikawa, Akira Takata, Takashi Sawada
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Patent number: 5738731Abstract: A solar cell comprising:a first junction part having a first conductivity type first semiconductor film and a second conductivity type second semiconductor film formed on an upper surface of said first semiconductor film; anda second junction part having a first conductivity type third semiconductor film formed on an upper surface of said second semiconductor film and a second conductivity type fourth semiconductor formed on an upper surface of said third semiconductor film,said junction parts arranged from that having a larger forbidden band width along the direction of progress of light through said semiconductor layers,said first, second, third, and fourth semiconductor films being formed of single-crystalline filming;wherein an interlayer conductor prepared from a metal forming ohmic junctions with each of said junction parts and having a thickness capable of transmitting light therethrough is interposed between said first and second junction parts; andwherein said second semiconductor film arranged on onType: GrantFiled: August 31, 1994Date of Patent: April 14, 1998Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 5700975Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.Type: GrantFiled: March 28, 1995Date of Patent: December 23, 1997Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5666304Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.Type: GrantFiled: February 28, 1996Date of Patent: September 9, 1997Assignee: Mega Chips CorporationInventors: Tetsuo Hikawa, Akira Takata, Takashi Sawada
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Patent number: 5640367Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.Type: GrantFiled: February 28, 1996Date of Patent: June 17, 1997Assignee: Mega Chips CorporationInventors: Tetsuo Hikawa, Akira Takata, Takashi Sawada
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Patent number: 5563844Abstract: In order to improve area efficiency of a mask ROM, a head address is inputted from a common pad (204) only in an initial access, so that addresses are thereafter changed by an internal counter (212). Data output is carried out through the common pad (204). Wires are employed for address input and data output in common, thereby remarkably reducing the number of wires.Type: GrantFiled: March 28, 1995Date of Patent: October 8, 1996Assignees: Mega Chips Corporation, Tom Dang-hsing YiuInventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
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Patent number: 5526306Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming several of types of memory cells having different electrical properties. Storage data per memory cell is therefore so multivalued that the number of memory cells is reduced.Type: GrantFiled: June 7, 1994Date of Patent: June 11, 1996Assignee: Mega Chips CorporationInventors: Tetsuo Hikawa, Akira Takata, Takashi Sawada
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Patent number: 5031019Abstract: A method for manufacturing a Bi-CMOS device by preparing both of bipolar and MOS standard cells in a library is provided. A substrate of a first conductivity type is provided and a plurality of buried layers of a second conductivity type are formed on selected locations of the substrate. Then an epitaxial layer of the first conductivity type is formed on the substrate covering the buried layers. Then a plurality of wells of the second conductivity type are formed in the epitaxial layer such that each of the wells extends through the epitaxial layer from the top surface to at least a portion of the corresponding buried layer to thereby define a plurality of electrically isolated islands in the epitaxial layer. Then a bipolar transistor is formed in at least one of the islands with a MOS transistor formed in at least another of the islands.Type: GrantFiled: May 27, 1988Date of Patent: July 9, 1991Assignee: Ricoh Company, Ltd.Inventors: Daisuke Kosaka, Yoshinori Ueda, Tetsuo Hikawa, Masami Nishikawa
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Patent number: 4634494Abstract: The etch rate of phosphosilicate glass becomes lowered as boron ions are implanted therein. In accordance with the principle of the present invention, boron ions are implanted into a phosphosilicate glass film selectively in location or concentration and the thus boron-implanted phosphosilicate glass film is etched by an etchant, for example buffered hydrofluoric acid solution, to etch an intended portion of the phosphosilcate glass film preferentially thereby defining a hole, such as a contact hole, or substantially flat surface.Type: GrantFiled: July 29, 1985Date of Patent: January 6, 1987Assignee: Ricoh Company, Ltd.Inventors: Satoru Taji, Norio Yoshida, Tetsuo Hikawa