Patents by Inventor Tetsuo Hirakawa

Tetsuo Hirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6787706
    Abstract: A ceramic circuit board that protects a metallized wiring layer from fusion when a large electric current is applied thereto. The ceramic circuit board includes a ceramic substrate, a plurality of metallized wiring layers formed on the ceramic substrate, and a metal circuit plate made of copper, which is attached to part of the metallized wiring layers. The condition, S≧6×10−5i2, is fulfilled in the ceramic circuit board, whereby S (mm2) is the sectional area of the metal circuit plate and i (A) the value of a flowing electric current.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: September 7, 2004
    Assignee: Kyocera Corporation
    Inventor: Tetsuo Hirakawa
  • Publication number: 20020112882
    Abstract: It is an object of the invention to protect a metallized wiring layer from fusion when a large electric current is applied thereto. A ceramic circuit board comprises: a ceramic substrate; a plurality of metallized wiring layers formed on the ceramic substrate; and a metal circuit plate made of copper, which is attached to part of the metallized wiring layers. In the ceramic circuit board, assuming that a sectional area of the metal circuit plate is S (mm2) and that a value of a flowing electric current is i (A), a condition: S≧6×10−5 i2 is fulfilled.
    Type: Application
    Filed: February 19, 2002
    Publication date: August 22, 2002
    Applicant: KYOCERA CORPORATION
    Inventor: Tetsuo Hirakawa
  • Patent number: 5883428
    Abstract: A semiconductor element-housing package, comprising an insulating substrate composed of a plurality of laminated insulating layers and having a mounting portion for mounting a semiconductor element, in the center of a top surface thereof; a ground bonding pad and a power-supply bonding pad formed on the top surface of the insulating substrate, at the periphery of the semiconductor element-mounting portion, to which a ground electrode and a power-supply electrode of the semiconductor element are connected; and a pair of capacitor-connecting pads, formed on the underside of the insulating substrate, one of which is connected to the ground bonding pad, the other of which is connected to the power-supply bonding pad, and to both of which electrodes of a chip capacitor are connected, characterized by having a ground plane and a power-supply plane sandwiching at least one of the insulating layers buried opposing each other within the insulating substrate, and having electrical connections from the ground plane and
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: March 16, 1999
    Assignee: Kyocera Corporation
    Inventors: Masanao Kabumoto, Masaaki Hori, Tetsuo Hirakawa
  • Patent number: 5652466
    Abstract: A package for housing a semiconductor element is provided which allows effective prevention of adverse effects of power supply noise on the semiconductor, and normal and steady operation of the semiconductor element over a long period of time. The package for housing a semiconductor element is assembled by forming connection pads, which are connected to the power supply electrode and the grounding electrode of the semiconductor element to be housed therein, on the outer surface of a container having a space for housing the semiconductor element therein and attaching electrodes of a capacitor element to the connection pads by means of a soldering material. The soldering material is formed of an alloy consisting of from 40.0 to 45.0% by weight of silver, from 5.0 to 45.0% by weight of indium, from 15.0 to 55.0% by weight of tin, and 10.0% or less by weight of copper.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: July 29, 1997
    Assignee: Kyocera Corporation
    Inventors: Tetsuo Hirakawa, Kozo Matsukawa