Patents by Inventor Tetsuo Hiraki

Tetsuo Hiraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9729626
    Abstract: A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 8, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Naoki Odate, Tetsuo Hiraki
  • Patent number: 9672076
    Abstract: A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: June 6, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo
  • Patent number: 9635671
    Abstract: A scheduling method includes acquiring first information, second information, and third information from a first terminal located in a service area of a first base station; determining based on the first information, the second information, and the third information, whether a first process assigned to the first terminal is to be collected; and assigning the first process to a second terminal located in the service area of the first base station, when at the determining the first process is determined to be collected.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: April 25, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Tetsuo Hiraki
  • Patent number: 9588817
    Abstract: A scheduling method executed by a scheduler that manages multiple processors, includes detecting based on an application information table when a first application is started up, a processor that executes a second application that is not executed concurrently with the first application; and assigning the first application to the processor.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Tetsuo Hiraki, Koji Kurihara, Toshiya Otomo
  • Patent number: 9563465
    Abstract: A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki
  • Publication number: 20160334854
    Abstract: A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Toshiya Otomo, Naoki ODATE, Tetsuo HIRAKI
  • Patent number: 9483101
    Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: November 1, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo
  • Patent number: 9471123
    Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 18, 2016
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Hiraki, Hiromasa Yamauchi, Koichiro Yamashita, Fumihiko Hayakawa, Naoki Odate, Takahisa Suzuki, Koji Kurihara
  • Publication number: 20140282588
    Abstract: A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit.
    Type: Application
    Filed: September 16, 2013
    Publication date: September 18, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa SUZUKI, Koichiro YAMASHITA, Hiromasa YAMAUCHI, Koji KURIHARA, Fumihiko HAYAKAWA, Naoki ODATE, Tetsuo HIRAKI, Toshiya OTOMO
  • Publication number: 20140201546
    Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 17, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuo HIRAKI, Hiromasa Yamauchi, Koichiro Yamashita, Fumihiko Hayakawa, Naoki Odate, Takahisa Suzuki, Koji Kurihara
  • Publication number: 20140012921
    Abstract: A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal.
    Type: Application
    Filed: September 13, 2013
    Publication date: January 9, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Naoki Odate, Tetsuo Hiraki
  • Publication number: 20140006666
    Abstract: A task scheduling method is executed by a multi-core system and includes reading from a profile memory, first information concerning operation of a first task in a single core system; calculating second information concerning operation of a second task in the multi-core system, based on the first information; and setting based on the second information, an operating environment of a core that executes the second task.
    Type: Application
    Filed: September 6, 2013
    Publication date: January 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuo HIRAKI, Hiromasa YAMAUCHI, Koichiro YAMASHITA, Fumihiko HAYAKAWA, Naoki ODATE, Takahisa SUZUKI, Koji KURIHARA
  • Publication number: 20130326527
    Abstract: A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process.
    Type: Application
    Filed: August 9, 2013
    Publication date: December 5, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa SUZUKI, Koichiro YAMASHITA, Hiromasa YAMAUCHI, Koji KURIHARA, Toshiya OTOMO, Naoki ODATE, Tetsuo HIRAKI
  • Publication number: 20130311751
    Abstract: A system includes plural processors; memory that stores a program currently under execution by the processors; and a pre-loader that pre-loads into a fragment area of the memory, a target program that is to be executed and is a program other than the program currently under execution by the processors.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Koji KURIHARA, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Fumihiko HAYAKAWA, Naoki ODATE, Tetsuo HIRAKI, Toshiya OTOMO
  • Publication number: 20130312002
    Abstract: A scheduling method executed by a scheduler that manages multiple processors, includes detecting based on an application information table when a first application is started up, a processor that executes a second application that is not executed concurrently with the first application; and assigning the first application to the processor.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Tetsuo Hiraki, Koji Kurihara, Toshiya Otomo
  • Publication number: 20130305251
    Abstract: A scheduling method is performed by a scheduler that manages plural processors including a first processor and a second processor. The scheduling method includes assigning an application to the first processor when the application is started; instructing the second processor to calculate load of the processors; and maintaining assignment of the application or changing assignment of the application based on the load.
    Type: Application
    Filed: July 18, 2013
    Publication date: November 14, 2013
    Inventors: Hiromasa YAMAUCHI, Koichiro Yamashita, Tetsuo Hiraki, Koji Kurihara, Toshiya Otomo
  • Publication number: 20130303221
    Abstract: A scheduling method includes acquiring first information, second information, and third information from a first terminal located in a service area of a first base station; determining based on the first information, the second information, and the third information, whether a first process assigned to the first terminal is to be collected; and assigning the first process to a second terminal located in the service area of the first base station, when at the determining the first process is determined to be collected.
    Type: Application
    Filed: July 12, 2013
    Publication date: November 14, 2013
    Inventors: Toshiya OTOMO, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Koji KURIHARA, Tetsuo HIRAKI
  • Publication number: 20130298137
    Abstract: A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time.
    Type: Application
    Filed: July 3, 2013
    Publication date: November 7, 2013
    Inventors: Hiromasa YAMAUCHI, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki
  • Publication number: 20130275790
    Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.
    Type: Application
    Filed: June 12, 2013
    Publication date: October 17, 2013
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo