Patents by Inventor Tetsuo Hiraki
Tetsuo Hiraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9729626Abstract: A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal.Type: GrantFiled: September 13, 2013Date of Patent: August 8, 2017Assignee: FUJITSU LIMITEDInventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Naoki Odate, Tetsuo Hiraki
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Patent number: 9672076Abstract: A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit.Type: GrantFiled: September 16, 2013Date of Patent: June 6, 2017Assignee: FUJITSU LIMITEDInventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo
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Patent number: 9635671Abstract: A scheduling method includes acquiring first information, second information, and third information from a first terminal located in a service area of a first base station; determining based on the first information, the second information, and the third information, whether a first process assigned to the first terminal is to be collected; and assigning the first process to a second terminal located in the service area of the first base station, when at the determining the first process is determined to be collected.Type: GrantFiled: July 12, 2013Date of Patent: April 25, 2017Assignee: FUJITSU LIMITEDInventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Tetsuo Hiraki
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Patent number: 9588817Abstract: A scheduling method executed by a scheduler that manages multiple processors, includes detecting based on an application information table when a first application is started up, a processor that executes a second application that is not executed concurrently with the first application; and assigning the first application to the processor.Type: GrantFiled: July 19, 2013Date of Patent: March 7, 2017Assignee: FUJITSU LIMITEDInventors: Hiromasa Yamauchi, Koichiro Yamashita, Tetsuo Hiraki, Koji Kurihara, Toshiya Otomo
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Patent number: 9563465Abstract: A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time.Type: GrantFiled: July 3, 2013Date of Patent: February 7, 2017Assignee: FUJITSU LIMITEDInventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki
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Publication number: 20160334854Abstract: A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Applicant: FUJITSU LIMITEDInventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Toshiya Otomo, Naoki ODATE, Tetsuo HIRAKI
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Patent number: 9483101Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.Type: GrantFiled: June 12, 2013Date of Patent: November 1, 2016Assignee: FUJITSU LIMITEDInventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo
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Patent number: 9471123Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.Type: GrantFiled: March 14, 2014Date of Patent: October 18, 2016Assignee: Fujitsu LimitedInventors: Tetsuo Hiraki, Hiromasa Yamauchi, Koichiro Yamashita, Fumihiko Hayakawa, Naoki Odate, Takahisa Suzuki, Koji Kurihara
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Publication number: 20140282588Abstract: A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit.Type: ApplicationFiled: September 16, 2013Publication date: September 18, 2014Applicant: FUJITSU LIMITEDInventors: Takahisa SUZUKI, Koichiro YAMASHITA, Hiromasa YAMAUCHI, Koji KURIHARA, Fumihiko HAYAKAWA, Naoki ODATE, Tetsuo HIRAKI, Toshiya OTOMO
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Publication number: 20140201546Abstract: A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU.Type: ApplicationFiled: March 14, 2014Publication date: July 17, 2014Applicant: FUJITSU LIMITEDInventors: Tetsuo HIRAKI, Hiromasa Yamauchi, Koichiro Yamashita, Fumihiko Hayakawa, Naoki Odate, Takahisa Suzuki, Koji Kurihara
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Publication number: 20140012921Abstract: A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal.Type: ApplicationFiled: September 13, 2013Publication date: January 9, 2014Applicant: FUJITSU LIMITEDInventors: Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Naoki Odate, Tetsuo Hiraki
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Publication number: 20140006666Abstract: A task scheduling method is executed by a multi-core system and includes reading from a profile memory, first information concerning operation of a first task in a single core system; calculating second information concerning operation of a second task in the multi-core system, based on the first information; and setting based on the second information, an operating environment of a core that executes the second task.Type: ApplicationFiled: September 6, 2013Publication date: January 2, 2014Applicant: FUJITSU LIMITEDInventors: Tetsuo HIRAKI, Hiromasa YAMAUCHI, Koichiro YAMASHITA, Fumihiko HAYAKAWA, Naoki ODATE, Takahisa SUZUKI, Koji KURIHARA
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Publication number: 20130326527Abstract: A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process.Type: ApplicationFiled: August 9, 2013Publication date: December 5, 2013Applicant: FUJITSU LIMITEDInventors: Takahisa SUZUKI, Koichiro YAMASHITA, Hiromasa YAMAUCHI, Koji KURIHARA, Toshiya OTOMO, Naoki ODATE, Tetsuo HIRAKI
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Publication number: 20130312002Abstract: A scheduling method executed by a scheduler that manages multiple processors, includes detecting based on an application information table when a first application is started up, a processor that executes a second application that is not executed concurrently with the first application; and assigning the first application to the processor.Type: ApplicationFiled: July 19, 2013Publication date: November 21, 2013Applicant: FUJITSU LIMITEDInventors: Hiromasa Yamauchi, Koichiro Yamashita, Tetsuo Hiraki, Koji Kurihara, Toshiya Otomo
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Publication number: 20130311751Abstract: A system includes plural processors; memory that stores a program currently under execution by the processors; and a pre-loader that pre-loads into a fragment area of the memory, a target program that is to be executed and is a program other than the program currently under execution by the processors.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: FUJITSU LIMITEDInventors: Koji KURIHARA, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Fumihiko HAYAKAWA, Naoki ODATE, Tetsuo HIRAKI, Toshiya OTOMO
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Publication number: 20130305251Abstract: A scheduling method is performed by a scheduler that manages plural processors including a first processor and a second processor. The scheduling method includes assigning an application to the first processor when the application is started; instructing the second processor to calculate load of the processors; and maintaining assignment of the application or changing assignment of the application based on the load.Type: ApplicationFiled: July 18, 2013Publication date: November 14, 2013Inventors: Hiromasa YAMAUCHI, Koichiro Yamashita, Tetsuo Hiraki, Koji Kurihara, Toshiya Otomo
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Publication number: 20130303221Abstract: A scheduling method includes acquiring first information, second information, and third information from a first terminal located in a service area of a first base station; determining based on the first information, the second information, and the third information, whether a first process assigned to the first terminal is to be collected; and assigning the first process to a second terminal located in the service area of the first base station, when at the determining the first process is determined to be collected.Type: ApplicationFiled: July 12, 2013Publication date: November 14, 2013Inventors: Toshiya OTOMO, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Koji KURIHARA, Tetsuo HIRAKI
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Publication number: 20130298137Abstract: A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time.Type: ApplicationFiled: July 3, 2013Publication date: November 7, 2013Inventors: Hiromasa YAMAUCHI, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki
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Publication number: 20130275790Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.Type: ApplicationFiled: June 12, 2013Publication date: October 17, 2013Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Fumihiko Hayakawa, Naoki Odate, Tetsuo Hiraki, Toshiya Otomo