Abstract: In an information processing system having a bus bridge connected between a plurality of buses for data transfer therebetween, the bus bridge is provided with a RAS data acquisition bus operating independently from the plurality of buses and a RAS data acquisition circuit for acquiring RAS data, the RAS data acquisition circuit acquires RAS data in the bus bridge or RAS data of a processor or an I/O device on a bus connected to the bus bridge, in response to a command supplied from an external circuit via the RAS data acquisition bus. The RAS data acquisition circuit sends the acquired RAS data to the external circuit via the RAS data acquisition bus.

Abstract: A plurality of processor elements (31 to 34) are disposed on a main board (710) in line in parallel with a first edge of the main substrate (710). Expansion board slots (331 to 336) into which an expansion board for mounting an I/O interface thereon is plugged and a memory connector (341) to which a memory board for mounting a memory thereon is connected are disposed in a region of the main substrate opposite to the first edge. The long sides of the expansion board slots (331 to 336) and the memory board connector (341) are in parallel with the first edge. A bridge LSI for executing protocol conversion between processor buses (210, 211, 212) and an I/O bus (230) and memory controllers (151, 152) for controlling memory access are disposed in regions adjacent to both the expansion board slots and the processor elements.