Patents by Inventor Tetsuo Ishiguro

Tetsuo Ishiguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7982217
    Abstract: A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Norihiko Sugita, Tetsuo Ishiguro, Naoki Yashiki
  • Publication number: 20100147804
    Abstract: An interrupting part 2 is arranged in a vessel 1 that is filled with insulating gas to configure a puffer type gas circuit breaker. The interrupting part 2 having, at least, a main contact 3, 6 on each of fixed- and moving-sides, an arcing contact 4, 7 on each of the fixed- and moving-sides, a puffing device, and an insulative nozzle 10. The insulating gas that became high temperature by being puffed into the arcs is discharged through a puffer shaft 11 of tubular shape. The puffer shaft 11 has a pipe member 11a at the distal end of which the arcing contact 7 is installed, and an end member 11b, one end of which is separably connected to the pipe member 11a with a joint 11 and the other end of which is connected to a rod 12 that links to a manipulator side.
    Type: Application
    Filed: June 2, 2008
    Publication date: June 17, 2010
    Applicant: JAPAN AE POWER SYSTEMS CORPORATION
    Inventors: Naoto Yamada, Makoto Hirose, Tetsuo Ishiguro
  • Publication number: 20080237592
    Abstract: A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module.
    Type: Application
    Filed: May 23, 2008
    Publication date: October 2, 2008
    Inventors: Norihiko Sugita, Tetsuo Ishiguro, Naoki Yashiki
  • Publication number: 20050099199
    Abstract: A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module.
    Type: Application
    Filed: December 26, 2001
    Publication date: May 12, 2005
    Inventors: Norihiko Sugita, Tetsuo Ishiguro, Naoki Yashiki