Patents by Inventor Tetsuo Kamada

Tetsuo Kamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scan-based integrated circuit having clock frequency divider
    Patent number: 8065549
    Abstract: An integrated circuit includes a clock generator and a synchronous clock circuit unit. The clock generator generates a first clock signal, a second clock signal, and a third clock signal, which are synchronized with one another and are provided with mutually different frequencies. The synchronous clock circuit unit includes synchronous clock circuits to which the first clock signal, the second clock signal, and the third clock signal are inputted, respectively. The synchronous clock circuits are scanned by use of the first clock signal, the second clock signal, and the third clock signal.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuo Kamada
  • Scan test circuit and method of arranging the same
    Patent number: 7584393
    Abstract: Replaced cell CELL1 is composed of clock buffer circuit CB1 and flip-flop circuit FF1 that latches data at a falling-down time of a clock signal. Clock buffer circuits CB1a-CB1d are cascade-connected to form a clock tree circuit. A scan circuit is composed of scan flip-flop circuits SFF1-SFF4. Replaced cell CELL1 is set in place of the last stage neighboring a scan circuit side between the scan circuit and the clock buffer circuits CB1a-CB1d to easily optimize timing adjustments and layout design.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: September 1, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Kamada, Toru Sasaki, Hiroshi Shimizu
  • SCAN-BASED INTEGRATED CIRCUIT
    Publication number: 20080115005
    Abstract: An integrated circuit includes a clock generator and a synchronous clock circuit unit. The clock generator generates a first clock signal, a second clock signal, and a third clock signal, which are synchronized with one another and are provided with mutually different frequencies. The synchronous clock circuit unit includes synchronous clock circuits to which the first clock signal, the second clock signal, and the third clock signal are inputted, respectively. The synchronous clock circuits are scanned by use of the first clock signal, the second clock signal, and the third clock signal.
    Type: Application
    Filed: November 8, 2007
    Publication date: May 15, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tetsuo Kamada
  • SCAN TEST CIRCUIT AND METHOD OF ARRANGING THE SAME
    Publication number: 20070011524
    Abstract: Replaced cell CELL1 is composed of clock buffer circuit CB1 and flip-flop circuit FF1 that latches data at a falling-down time of a clock signal. Clock buffer circuits CB1a-CB1d are cascade-connected to form a clock tree circuit. A scan circuit is composed of scan flip-flop circuits SFF1-SFF4. Replaced cell CELL1 is set in place of the last stage neighboring a scan circuit side between the scan circuit and the clock buffer circuits CB1a-CB1d to easily optimize timing adjustments and layout design.
    Type: Application
    Filed: June 2, 2006
    Publication date: January 11, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Kamada, Toru Sasaki, Hiroshi Shimizu