Abstract: The disclosure relates to an image processing apparatus, the image processing apparatus including: an image signal receiver configured to receive an image signal; a first preprocessor configured to sequentially processes a predetermined section of the received image signal and generate a first intermediate signal; a second preprocessor arranged in parallel with the first preprocessor and configured to sequentially process another section of the image signal and generate a second intermediate signal; a storage configured to store the first intermediate signal and the second intermediate signal; and a postprocessor configured to perform signal processing with regard to the first and second intermediate signals stored in the storage, the size of the section being corresponding to processing speeds of the first and second preprocessors and a processing speed of the postprocessor.

Abstract: Provided are a method and apparatus for processing a division operation. The method includes acquiring input data, detecting reference data related to a division operation corresponding to the acquired input data, from a cache memory in which data related to at least one division operation is pre-stored, selecting any one operator from among a plurality of operators identified according to at least one of a processable number of data bits and a calculation type, based on a difference between the detected reference data and the input data, and acquiring a result of performing division operation on the input data from the selected operator.

Abstract: The disclosure relates to an image processing apparatus, the image processing apparatus including: an image signal receiver configured to receive an image signal; a first preprocessor configured to sequentially processes a predetermined section of the received image signal and generate a first intermediate signal; a second preprocessor arranged in parallel with the first preprocessor and configured to sequentially process another section of the image signal and generate a second intermediate signal; a storage configured to store the first intermediate signal and the second intermediate signal; and a postprocessor configured to perform signal processing with regard to the first and second intermediate signals stored in the storage, the size of the section being corresponding to processing speeds of the first and second preprocessors and a processing speed of the postprocessor.

Abstract: Provided are a method and apparatus for processing a division operation. The method includes acquiring input data, detecting reference data related to a division operation corresponding to the acquired input data, from a cache memory in which data related to at least one division operation is pre-stored, selecting any one operator from among a plurality of operators identified according to at least one of a processable number of data bits and a calculation type, based on a difference between the detected reference data and the input data, and acquiring a result of performing division operation on the input data from the selected operator.

Abstract: A processor includes a first encoder configured to encode a regular bin block including at least one regular bin, a second encoder configured to encode a bypass bin block including at least one bypass bin, and a parameter calculating module comprising parameter calculating circuitry configured to determine context information for encoding the regular bin block and to transmit the context information to the first encoder. The first encoder and the second encoder may process the regular bin block and the bypass bin block simultaneously and in parallel during at least part of a specific processing cycle.

Abstract: A processor includes a first encoder configured to encode a regular bin block including at least one regular bin, a second encoder configured to encode a bypass bin block including at least one bypass bin, and a parameter calculating module comprising parameter calculating circuitry configured to determine context information for encoding the regular bin block and to transmit the context information to the first encoder. The first encoder and the second encoder may process the regular bin block and the bypass bin block simultaneously and in parallel during at least part of a specific processing cycle.

Abstract: When data is an HDTV signal, a buffer memory is used as two banks and pipeline processing is performed. When data is an SDTV signal, on the other hand, the buffer memory is used as a bankless buffer memory, and the pipeline processing is not performed.

Abstract: A data storage/reading circuit successively stores frame data in a data storage memory. A start address storage unit memorizes a start address of non-reference frame data stored in the data storage memory. A decoding circuit starts a decoding operation by reading the data from the start address of already stored non-reference frame data, based on a decoding start command.

Abstract: Input bits having a predetermined number of bits are divided into a plurality of bits by a bit dividing apparatus. Several of the divided bits are input into a recording apparatus, and are converted into address information. The data subjected to variable length decoding and a number of bits of the data are output from the recording apparatus according to the output of the recording apparatus. A plurality of kinds of variable length decoding are performed by rewriting the table of the recording apparatus.

Abstract: Input bits having a predetermined number of bits are divided into a plurality of bits by a bit dividing apparatus. Several of the divided bits are input into a recording apparatus, and are converted into address information. The data subjected to variable length decoding and a number of bits of the data are output from the recording apparatus according to the output of the recording apparatus. A plurality of kinds of variable length decoding are performed by rewriting the table of the recording apparatus.

Abstract: A data storage/reading circuit successively stores frame data in a data storage memory. A start address storage unit memorizes a start address of non-reference frame data stored in the data storage memory. A decoding circuit starts a decoding operation by reading the data from the start address of already stored non-reference frame data, based on a decoding start command.

Abstract: When data is an HDTV signal, a buffer memory is used as two banks and pipeline processing is performed. When data is an SDTV signal, on the other hand, the buffer memory is used as a bankless buffer memory, and the pipeline processing is not performed.

Abstract: A frame memory successively stores post-filter data in such a manner that 1-column/1-row pre-filter data extending along the right and lower sides of each block are not overwritten by the post-filter data. Thus, the frame memory stores both the post-filter data used for inter-prediction and the pre-filter data remaining for intra-prediction of a next block. The inter-prediction and the intra-prediction can be simultaneously executed based on the data stored in the frame memory.