Abstract: A video chroma signal processing circuit in which a composite video signal, formed of an analog luminance signal and an analog chrominance signal, is separated into Y and C components and converted into digital codes by AD converters and processed by processing circuits. The outputs of the processing circuits are converted into analog signals again with DA converters to produce a picture image; wherein, it is intended to obtain a wide band of a luminance signal by making efficient use of an AD converter for a chrominance signal and to improve horizontal resolution. The apparent sampling frequency is doubled by sampling the AD converter for a chrominance signal with a phase reverse to that of an AD converter for a luminance signal so as to improve the horizontal resolution of the luminance signal.

Abstract: An apparatus for receiving and selecting high-definition television signals and NTSC standard television signals includes a high-definition display screen device having an aspect ratio of 16 to 9. The NTSC standard television signals have an aspect ratio which is different than the 16 to 9 aspect ratio of the high-definition display screen device. A first signal converter is for converting the NTSC standard television signals into first quasi-high-definition television signals identifying a first displayed image corresponding in vertical length to a vertical length of the high-definition display screen device. A second signal converter is for converting the NTSC standard television signals into second quasi-high-definition television signals identifying a second displayed image corresponding in horizontal length to a horizontal length of the high-definition display screen device.

Abstract: An analog-to-digital converter converts an input analog video signal into a corresponding digital video signal. A first input terminal of a phase comparator receives the digital video signal. A loop filter receives an output signal from the phase comparator. A digital-to-analog converter converts an output signal from the loop filter into a corresponding analog control signal. First and second voltage-controlled oscillators generate oscillation output signals having different frequencies respectively which depend on the analog control signal. A switch selects and outputs either of the oscillation output signals. A frequency divider divides a frequency of the selected oscillation output signal into a value corresponding to a horizontal frequency. The frequency divider supplies its output signal to a second input terminal of the phase comparator.

Abstract: Disclosed is a local oscillator using a dielectric coaxial resonator (27), which is availably used as a fixed local oscillator in double-spot tuners and CATV converters, and which is arranged so that an AFC voltage is applied to a variable-capacitance diode (23) from an output terminal (E) of a frequency control circuit through a first resistor (35), the variable-capacitance diode having its one end being connected to a center conductor of a dielectric coaxial resonator (27) through a capacitor (25) and its other end being AC grounded, and that a first reference potential (V.sub.A) lower than a source voltage (V.sub.CC) by a predetermined value is given to the variable-capacitance diode (23), the one end of the variable-capacitance diode (23) being connected to the source voltage (V.sub.

Abstract: In a synchronous video detector circuit using a phase-locked loop, the synchronous detection of a video IF signal is effected with a synchronous carrier signal reproduced by the PLL including a voltage-controlled oscillator. Each of a phase comparator of the PLL and a synchronous video detector has its input terminal connected to an output terminal of a video IF amplifier by untuned coupling, and arranged on the output side of the synchronous video detector is a phase-locked mode detector for detecting that the PLL is in its phase-locked mode. The phase-locked mode detector is adapted to control the band width of a low-pass filter of the PLL in either a narrow band mode or a wide band mode and the low-pass filter is controlled to operate in the narrow band mode only when the PLL is in the phase-locked mode of operation.