Abstract: For preventing an input signal supplied to an input terminal (A) from directly affecting an inverted signal derived at a node (15), an inverter stage of an inverter-buffer circuit composed of MOS transistors comprises two additional partial inverter stages (Q.sub.6 -Q.sub.5 and Q.sub.7 -Q.sub.8) between a buffer stage (Q.sub.3 -Q.sub.4) and a conventional inverter stage (Q.sub.1 -Q.sub.2) that serves now as an input-side partial inverter stage. The buffer stage favorably comprises an additional MOS transistor (Q.sub.9) having a gate connected directly to the node in order to achieve a short switching delay.

Abstract: A boot strap type circuit which can raise an output potential up to a power supply voltage irrespective of a condition of an input signal is disclosed. The circuit is characterized by comprising a series circuit coupled between a first end of a capacitor, from which end a boot strapped voltage is derived, and a reference voltage, the series circuit being responsive to transition of the input signal for pulling down a potential at the first end of the capacitor after a predetermined delay from that transition.

Abstract: A memory device which is stable in operation and operable at high speed is disclosed. The memory device comprises a plurality of pairs of digit lines, a plurality of sense amplifiers having a pair of input terminals, a plurality of pairs of gating means and a plurality of memory cells and is characterized in that the pair of input terminals of the sense amplifiers are operatively coupled through the pair of gating means to the pair of digit lines.

Abstract: For preventing an input signal supplied to an input terminal (A) from directly affecting an inverted signal derived at a node (15), an inverter stage of an inverter-buffer circuit composed of MOS transistors comprises two additional partial inverter stages (Q.sub.6 -Q.sub.5 and Q.sub.7 -Q.sub.8) between a buffer stage (Q.sub.3 -Q.sub.4) and a conventional inverter stage (Q.sub.1 -Q.sub.2) that serves now as an input-side partial inverter stage. The buffer stage favorably comprises an additional MOS transistor (Q.sub.9) having a gate connected directly to the node in order to achieve a short switching delay.