Patents by Inventor Tetsuo Nomoto
Tetsuo Nomoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9490291Abstract: A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: June 23, 2015Date of Patent: November 8, 2016Assignee: SONY CORPORATIONInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20150334270Abstract: A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: ApplicationFiled: June 23, 2015Publication date: November 19, 2015Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Patent number: 9129879Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: September 24, 2013Date of Patent: September 8, 2015Assignee: SONY CORPORATIONInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20150249798Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (OV), and a negative power source potential (for example ?1V).Type: ApplicationFiled: February 26, 2015Publication date: September 3, 2015Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20140022428Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: ApplicationFiled: September 24, 2013Publication date: January 23, 2014Applicant: Sony CorporationInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi
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Patent number: 8558932Abstract: A MOS type solid state imaging device having unit pixels, each having a photodiode a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: November 14, 2011Date of Patent: October 15, 2013Assignee: Sony CorporationInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20120105698Abstract: A MOS type solid state imaging device having unit pixels, each having a photodiode a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: ApplicationFiled: November 14, 2011Publication date: May 3, 2012Applicant: SONY CORPORATIONInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Patent number: 8072528Abstract: A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: November 30, 2009Date of Patent: December 6, 2011Assignee: Sony CorporationInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20100073536Abstract: A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: ApplicationFiled: November 30, 2009Publication date: March 25, 2010Applicant: SONY CORPORATIONInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Patent number: 7626625Abstract: A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: GrantFiled: September 16, 2004Date of Patent: December 1, 2009Assignee: Sony CorporationInventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
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Publication number: 20070024726Abstract: A solid state imaging device able to make noise from a nonselected row small, able to suppress occurrence of vertical stripes in a bright scene, not requiring charging including a floating node capacity via a reset transistor, able to prevent an increase of a driver size of a drain line, and able to secure high speed operation and a camera system using this as the imaging device are provided. An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).Type: ApplicationFiled: September 16, 2004Publication date: February 1, 2007Inventors: Tetsuo Nomoto, Eiji Makino
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Patent number: 6781802Abstract: A controlling device of a compressor is provided. A noise filter is arranged at an input of the inverter circuit that converts the commercial frequency to a driving frequency to control a motor driving a compressor mechanism, for suppressing a common mode noise of the commercial power source and the inverter circuit, and is connected to a ground through a metal frame used for receiving a compressor main body. The noise filter comprises coils connected between first capacitors and second capacitors that are connected in series between the AC power lines, and further comprises a clamper connected between nodes of the second capacitors and the metal frame for clamping a voltage and a third capacitor connected to the clamper in parallel. even though the new refrigerant, such as R410A, and the three-phase AC power source are used, the leakage current can be reduced by a simple structure and the increase of the noise terminal voltage can be also suppressed.Type: GrantFiled: September 16, 2002Date of Patent: August 24, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Hideaki Kato, Tetsuo Nomoto, Yuichi Izawa, Takahisa Matsuo, Yasuhiro Makino, Kazuhisa Otagaki
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Patent number: 6683799Abstract: An apparatus for protecting an inverter against over current is constructed of a plurality of switching devices connected between the positive and negative terminals of a DC power source. The apparatus has a plurality of detecting devices that convert the currents passing through the plurality of switching devices into voltages and generate detection outputs, a plurality of amplifier circuits, a plurality of comparing devices that supply the detection outputs of the detecting devices to the amplifier circuits and generate an abnormality output if an absolute value of a detection output exceeds a predetermined value, and a protecting device that interrupts the drive of all switching devices if any of the comparing devices issues an abnormality output.Type: GrantFiled: April 2, 2002Date of Patent: January 27, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Hideaki Kato, Takashi Ogawa, Tetsuo Nomoto, Yuichi Izawa
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Publication number: 20030117753Abstract: An apparatus for protecting an inverter constructed of a plurality of switching devices connected between an anode and a cathode of a DC power source allows secure protection of the inverter against overcurrent to be achieved at lower cost. The apparatus is provided with a plurality of detecting devices that convert the currents passing through the plurality of switching devices into voltages and generate detection outputs, a plurality of amplifier circuits, a plurality of comparing devices that supply the detection outputs of the detecting devices to the amplifier circuits and generate an abnormality output if an absolute value of a detection output exceeds a predetermined value, and a protecting device that interrupts the drive of all switching devices if any of the comparing devices issues an abnormality output.Type: ApplicationFiled: April 2, 2002Publication date: June 26, 2003Applicant: Sanyo Electric Co., Ltd.Inventors: Hideaki Kato, Takashi Ogawa, Tetsuo Nomoto, Yuichi Izawa
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Publication number: 20030079486Abstract: A controlling device of a compressor is provided. A noise filter is arranged at an input of the inverter circuit that converts the commercial frequency to a driving frequency to control a motor driving a compressor mechanism, for suppressing a common mode noise of the commercial power source and the inverter circuit, and is connected to a ground through a metal frame used for receiving a compressor main body. The noise filter comprises coils connected between first capacitors and second capacitors that are connected in series between the AC power lines, and further comprises a clamper connected between nodes of the second capacitors and the metal frame for clamping a voltage and a third capacitor connected to the clamper in parallel. even though the new refrigerant, such as R410A, and the three-phase AC power source are used, the leakage current can be reduced by a simple structure and the increase of the noise terminal voltage can be also suppressed.Type: ApplicationFiled: September 16, 2002Publication date: May 1, 2003Applicant: SANYO ELECTRIC CO., LTD.Inventors: Hideaki Kato, Tetsuo Nomoto, Yuichi Izawa, Takahisa Matsuo, Yasuhiro Makino, Kazuhisa Otagaki
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Patent number: 6538404Abstract: A motor apparatus, such as a DC brushless motor, is provided for the obtaining a position detection signal by detecting the intersection of the divided voltage of a bus voltage and three phases of the divided voltage of the three phases by a comparator which results in the central position of a flat portion. For the divided voltage for the three phases of the respective positive terminal of the comparator, the comparison voltage obtained by dividing the voltage between the divided voltage for the three phases of the following phase in the order and the divided voltage of the bus voltage is applied to the respective negative terminal. As the comparison voltage is phase shifted, the position can be detected by making a slant position ahead of the flat point of the intersection.Type: GrantFiled: February 13, 2001Date of Patent: March 25, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Hideaki Kato, Takashi Ogawa, Tetsuo Nomoto, Yuuichi Izawa
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Patent number: 6508636Abstract: A freon compressor comprises a compressor device and an electromotor device. The electromotor device is used for driving the compressor device and consists of a stator and a rotor rotating within the stator. The stator further consists of a stator core and stator windings wired on the stator core, and a three-phase sine alternating current waveform is applied to the stator windings. Therefore, the magnetic lines of force of the electromotor device are stabilized in space and time and noise is significantly reduced.Type: GrantFiled: January 17, 2001Date of Patent: January 21, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Ogawa, Hideaki Kato, Tetsuo Nomoto, Yuuichi Izawa
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Publication number: 20010026764Abstract: A freon compressor comprises a compressor device and an electromotor device. The electromotor device is used for driving the compressor device and consists of a stator and a rotor rotating within the stator. The stator further consists of a stator core and stator windings wired on the stator core, and a three-phase sine alternating current waveform is applied to the stator windings. Therefore, the magnetic lines of force of the electromotor device are stabilized in space and time and noise is significantly reduced.Type: ApplicationFiled: January 17, 2001Publication date: October 4, 2001Inventors: Takashi Ogawa, Hideaki Kato, Tetsuo Nomoto, Yuuichi Izawa
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Publication number: 20010019249Abstract: The position detection signal Su, Sv, Sw obtained by detecting the intersection of the divided voltage E0 of the bus voltage and the divided voltage Ua, Va, Wa of the three phases U, V, W by the comparator CPu, CPv, CPw results in the central position of the flat portion. For the divided voltage Ua, Va, Wa of respective +terminal of the comparator CPu, CPv, CPw, the comparison voltage Evs, Ews, Eus obtained by dividing the voltage between the divided voltage Ua, Va, Wa of the following phase in the order and the divided voltage E0 is applied to respective −terminal. As the comparison voltage is phase shifted, the position can be detected by making a slant position ahead of the flat point the intersection.Type: ApplicationFiled: February 13, 2001Publication date: September 6, 2001Inventors: Hideaki Kato, Takashi Ogawa, Tetsuo Nomoto, Yuuichi Izawa
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Patent number: 5909247Abstract: An XY-address solid-state image pickup apparatus comprises a pixel array made up a plurality of pixels two-dimensionally arranged and horizontal and vertical scanning circuits for reading the signal from the pixel array. Each scanning circuit comprises a plurality of unit stages cascaded, each unit stage comprising a plurality of first shift register units cascaded and a single second shift register unit which is associated with the plurality of first shift register units and which is driven by a clock different from the clock that drives the plurality of first shift register units. Each unit stage further comprises a first switch and a second switch. The input to the first unit of the first shift register units is also fed to the second shift register unit via the first switch. The output of the second shift register unit is fed to each of the plurality of first register units within the unit stage via the second switch.Type: GrantFiled: November 19, 1996Date of Patent: June 1, 1999Assignee: Olympus Optical Co., Ltd.Inventors: Shigeru Hosokai, Tetsuo Nomoto, Shinichi Nakajima