Patents by Inventor Tetsuo OOMORI

Tetsuo OOMORI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240313723
    Abstract: A semiconductor device includes: an output terminal outputting an output voltage; a bipolar transistor outputting a collector current to an output node; a bias current generation part including a first node, a first constant current source, and a first transistor connected in parallel with the first constant current source, and generating a bias current; a differential input part including a differential pair and a second node, in which the differential pair generates at the second node a control voltage according to a difference between the reference voltage and the voltage corresponding to the output voltage; and a drive part including a current supply circuit, a third node, and a second transistor controlling a potential of the third node according to the control voltage. The first transistor controls the bias current according to the control voltage.
    Type: Application
    Filed: March 13, 2024
    Publication date: September 19, 2024
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Tetsuo OOMORI
  • Patent number: 12047076
    Abstract: A semiconductor device includes: a first input to which an input signal is input; a second input to which a reference signal is input; and a comparison stage which includes a current source connected to a first potential and first and second current path parts connected between the current source and a second potential different from the first potential and performing a comparison operation in response to the input signal and the reference signal, wherein the first and second current path parts respectively include first and second input circuits which are connected to the current source and first and second load circuits which are connected between the second potential and the first and second input circuits, wherein the first input circuit includes a first signal transistor and a first reference transistor, and wherein the second input circuit includes a second signal transistor and a second reference transistor.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: July 23, 2024
    Assignee: LAPIS Technology Co., Ltd.
    Inventors: Shingo Taniguchi, Tetsuo Oomori
  • Publication number: 20240072745
    Abstract: A differential amplifier includes a first input terminal, second input terminals, output terminals, differential amplification circuits, and a current source circuit. The first input terminal is one of an inverting input terminal and a non-inverting input terminal. Each of the second input terminals is another of the inverting input terminal and the non-inverting input terminal. The output terminals output voltages respectively corresponding to the second input terminals. The differential amplification circuits are connected to the first input terminal and the second input terminals and are provided corresponding to the second input terminals. The current source circuit is connected to the differential amplification circuits. Each of the differential amplification circuits outputs an output voltage corresponding to a combination of a voltage inputted to the first input terminal and a voltage inputted to one of the second input terminals from a corresponding one of the output terminals.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 29, 2024
    Applicant: LAPIS Technology Co., Ltd.
    Inventors: Tetsuo OOMORI, Shingo TANIGUCHI
  • Publication number: 20230318583
    Abstract: A semiconductor device includes: a first input to which an input signal is input; a second input to which a reference signal is input; and a comparison stage which includes a current source connected to a first potential and first and second current path parts connected between the current source and a second potential different from the first potential and performing a comparison operation in response to the input signal and the reference signal, wherein the first and second current path parts respectively include first and second input circuits which are connected to the current source and first and second load circuits which are connected between the second potential and the first and second input circuits, wherein the first input circuit includes a first signal transistor and a first reference transistor, and wherein the second input circuit includes a second signal transistor and a second reference transistor.
    Type: Application
    Filed: March 22, 2023
    Publication date: October 5, 2023
    Applicant: LAPIS Technology Co., Ltd.
    Inventors: Shingo TANIGUCHI, Tetsuo OOMORI
  • Patent number: 11714440
    Abstract: A semiconductor device includes first to N-th voltage output circuits each outputting an output voltage and outputs a feedback voltage having a voltage value corresponding to the output voltage, and a differential circuit including first to N-th primary side transistors to which N feedback voltages are input and that individually flow first to N-th currents through a first node, a secondary side transistor that flows a reference current corresponding to a reference voltage through the first node, and a current mirror circuit as an active load. The current mirror circuit includes first to N-th primary side load transistors individually coupled in cascade to the first to N-th primary side transistors, a secondary side load transistor coupled in cascade to the secondary side transistor and generates a voltage at a connection point between the secondary side transistor and the secondary side load transistor as a control voltage.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: August 1, 2023
    Assignee: LAPIS TECHNOLOGY CO., LTD.
    Inventor: Tetsuo Oomori
  • Patent number: 11527994
    Abstract: An oscillator circuit includes an amplifying unit and a first feedback resistor. The amplifying unit includes an inverter at an input stage being connected to the one end of a crystal resonator, an inverter at an output stage being connected to the other end of the crystal resonator, and a linear amplifier. The linear amplifier is connected between an output terminal of the inverter at the input stage and an input terminal of the inverter at the output stage. The linear amplifier includes at least one inverter and a second feedback resistor. The second feedback resistor is connected in parallel to the at least one inverter. The linear amplifier has a conductance with a magnitude larger than a conductance of the inverter at the input stage and equal to or less than a conductance of the inverter at the output stage.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: December 13, 2022
    Assignee: LAPIS TECHNOLOGY CO., LTD.
    Inventor: Tetsuo Oomori
  • Publication number: 20220317711
    Abstract: A semiconductor device includes first to N-th voltage output circuits each outputting an output voltage and outputs a feedback voltage having a voltage value corresponding to the output voltage, and a differential circuit including first to N-th primary side transistors to which N feedback voltages are input and that individually flow first to N-th currents through a first node, a secondary side transistor that flows a reference current corresponding to a reference voltage through the first node, and a current mirror circuit as an active load. The current mirror circuit includes first to N-th primary side load transistors individually coupled in cascade to the first to N-th primary side transistors, a secondary side load transistor coupled in cascade to the secondary side transistor and generates a voltage at a connection point between the secondary side transistor and the secondary side load transistor as a control voltage.
    Type: Application
    Filed: March 23, 2022
    Publication date: October 6, 2022
    Inventor: TETSUO OOMORI
  • Publication number: 20220173698
    Abstract: An oscillator circuit includes an amplifying unit and a first feedback resistor. The amplifying unit includes an inverter at an input stage being connected to the one end of a crystal resonator, an inverter at an output stage being connected to the other end of the crystal resonator, and a linear amplifier. The linear amplifier is connected between an output terminal of the inverter at the input stage and an input terminal of the inverter at the output stage. The linear amplifier includes at least one inverter and a second feedback resistor. The second feedback resistor is connected in parallel to the at least one inverter. The linear amplifier has a conductance with a magnitude larger than a conductance of the inverter at the input stage and equal to or less than a conductance of the inverter at the output stage.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 2, 2022
    Inventor: TETSUO OOMORI
  • Patent number: 11070206
    Abstract: A logic circuit includes an inverter that outputs from an output terminal a signal created by inverting the logic of a signal input into an input terminal, a first transistor that is connected to the input terminal in such a way as to maintain an OFF state, and a second transistor that is connected to the output terminal in such a way as to maintain an OFF state.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: July 20, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuo Oomori
  • Patent number: 10958215
    Abstract: A semiconductor device includes a resistor element connected to one and another end of a crystal oscillator, and an adjustable current type inverter element having an input connected to one end of the resistor element and an output connected to another end of the resistor element. A first capacitor element is connected to the input of the inverter element and to ground, and a second capacitor element has one end connected to ground. A first switching element switches a connection state of the one end of the first capacitor element and another end of the second capacitor element. A third capacitor element is connected to the output of the inverter element and to ground, and a fourth capacitor element has one end connected to ground. A second switching element switches a connection state of the one end of the third capacitor element and another end of the fourth capacitor element.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuo Oomori
  • Publication number: 20200313673
    Abstract: A logic circuit includes an inverter that outputs from an output terminal a signal created by inverting the logic of a signal input into an input terminal, a first transistor that is connected to the input terminal in such a way as to maintain an OFF state, and a second transistor that is connected to the output terminal in such a way as to maintain an OFF state.
    Type: Application
    Filed: February 27, 2020
    Publication date: October 1, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Tetsuo OOMORI
  • Publication number: 20190305727
    Abstract: A semiconductor device including: a resistor element connected to one and another end of a crystal oscillator; an adjustable current type inverter element having an input connected to one end of the resistor element and an output connected to another end of the resistor element; a first capacitor element connected to the input of the inverter element and to ground; a second capacitor element having one end connected to ground; a first switching element that switches a connection state of the one end of the first capacitor element and another end of the second capacitor element; a third capacitor element connected to the output of the inverter element and to ground; a fourth capacitor element having one end connected to ground; and a second switching element that switches a connection state of the one end of the third capacitor element and another end of the fourth capacitor element.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventor: TETSUO OOMORI
  • Patent number: 10433420
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: October 1, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro Toda, Kenji Arai, Manabu Miyazawa, Kenichiro Nagatomo, Toru Ueno, Tsuguto Maruko, Hirofumi Ogawa, Tetsuo Oomori
  • Publication number: 20190261507
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro TODA, Kenji ARAI, Manabu MIYAZAWA, Kenichiro NAGATOMO, Toru UENO, Tsuguto MARUKO, Hirofumi OGAWA, Tetsuo OOMORI
  • Patent number: 10375819
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 6, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro Toda, Kenji Arai, Manabu Miyazawa, Kenichiro Nagatomo, Touru Ueno, Tsuguto Maruko, Hirofumi Ogawa, Tetsuo Oomori
  • Publication number: 20180242444
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 23, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro TODA, Kenji ARAI, Manabu MIYAZAWA, Kenichiro NAGATOMO, Touru UENO, Tsuguto MARUKO, Hirofumi OGAWA, Tetsuo OOMORI
  • Patent number: 8432223
    Abstract: A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal given to the two differential input elements. The differential amplifier circuit also includes an amplifying part for generating an output voltage generating signal by amplifying the differential signal. The differential amplifier circuit also includes an output part for generating an output voltage based on the output voltage generating signal and a power supply voltage.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: April 30, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Tetsuo Oomori
  • Publication number: 20120025912
    Abstract: A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal given to the two differential input elements. The differential amplifier circuit also includes an amplifying part for generating an output voltage generating signal by amplifying the differential signal. The differential amplifier circuit also includes an output part for generating an output voltage based on the output voltage generating signal and a power supply voltage.
    Type: Application
    Filed: July 26, 2011
    Publication date: February 2, 2012
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuo OOMORI