Patents by Inventor Tetsuo Sadamasa
Tetsuo Sadamasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5432812Abstract: A microcavity semiconductor laser disclosed therein includes a double-heterostructure section including an intermediate active layer sandwiched between a first or lower cladding layer and a second or upper cladding layer above a semiconductive substrate. A first multi-layered reflector section is arranged between the substrate and the double-heterostructure section to have its reflectance which becomes maximum near the oscillation wavelength of the laser. The upper cladding layer is semi-spherically formed. A three-dimensional optical reflector covers the double-heterostructure section, for controlling spontaneous emission obtained in the double-heterostructure section along various directions, and for increasing the coupling ratio of spontaneous emission with a specific laser mode, thereby to decrease the threshold current.Type: GrantFiled: July 12, 1993Date of Patent: July 11, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Kurobe, Tsutomu Tezuka, Tetsuo Sadamasa, Mitsuhiro Kushibe, Yoshita Kawakyu
-
Patent number: 5253262Abstract: A microcavity semiconductor laser disclosed therein includes a double-heterostructure section including an intermediate active layer sandwiched between a first or lower cladding layer and a second or upper cladding layer above a semiconductive substrate. A first multi-layered reflector section is arranged between the substrate and the double-heterostructure section to have its reflectance which becomes maximum near the oscillation wavelength of the laser. The upper cladding layer is semi-spherically formed. A three-dimensional optical reflector covers the double-heterostructure section, for controlling spontaneous emission obtained in the double-heterostructure section along various directions, and for increasing the coupling ratio of spontaneous emission with a specific laser mode, thereby to decrease the threshold current.Type: GrantFiled: October 30, 1991Date of Patent: October 12, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Kurobe, Tsutomu Tezuka, Tetsuo Sadamasa, Mitsuhiro Kushibe, Yoshito Kawakyu
-
Patent number: 5144381Abstract: A semiconductor light detector includes a first semiconductor layer of a first conductivity type having a multi-layer structure including a light absorbing layer and an avalanche multiplicating layer, an annular second semiconductor layer formed on the first semiconductor layer, a light detecting region formed by doping an impurity of a second conductivity type in a surface region of the first semiconductor layer, in such a manner that a peripheral portion of the light detecting region is located outside an inner periphery of the second semiconductor layer, the light detecting region defining a first p-n junction in combination with the first semiconductor layer, and a guard ring formed by doping an impurity of the second conductivity type in a surface region of the second semiconductor layer to surround the peripheral portion of the light receiving region with the first semiconductor layer, the second p-n junction having a concentration gradient lower than that of the first p-n junction.Type: GrantFiled: October 23, 1990Date of Patent: September 1, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Hideto Furuyama, Tetsuo Sadamasa
-
Patent number: 5084410Abstract: A semiconductor device which comprises a semiconductor substrate having a surface orientation substantially in a {100}-orientation is provided. On the semiconductor substrate, plural steps formed in a direction deviated substantially from a <110>-direction by 5 degrees or more are formed. The steps, which are mesa and concave portions, are buried by plural semiconductor crystal layers grown by the use of MOCVD or the like. A method of manufacturing such a device is also provided.Type: GrantFiled: October 14, 1988Date of Patent: January 28, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Eguchi, Tetsuo Sadamasa, Hideto Furuyama, Yuzo Hirayama
-
Patent number: 5001335Abstract: Disclosed are an avalanche photodiode and a manufacturing method thereof. An n.sup.- -type InGaAs light absorption layer and n.sup.- -type InP window layer are formed on an n-type InP substrate by crystal growth, in the order mentioned. A depression is formed in a selected surface portion of the window layer, and n-type impurities are doped into the bottom of the depression, to thereby form an n-type high concentration region. Further, n.sup.- -type crystal-grown InP layer is formed in the depression in such a way as to fill the depression. A guard ring is formed around the depression by the doping of p-type impurities. By doping p-type impurities into the window layer, a p-type high concentration region is formed in the window layer in a manner completely surrounding the interface between the n-type high concentration region and the crystal-grown InP layer. The n-type and p-type high concentration regions define a junction serving as a light-receiving region.Type: GrantFiled: December 29, 1989Date of Patent: March 19, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Keiji Takaoka, Tetsuo Sadamasa, Motoyasu Morinaga, Nobuo Suzuki, Kenji Matsumoto
-
Patent number: 4992386Abstract: A semiconductor light detector includes a first semiconductor layer of a first conductivity type having a multi-layer structure including a light absorbing layer and an avalanche multiplicating layer, an annular second semiconductor layer formed on the first semiconductor layer, a light detecting region formed by doping an impurity of a second conductivity type in a surface region of the first semiconductor layer, in such a manner that a peripheral portion of the light detecting region is located outside an inner periphery of the second semiconductor layer, the light deflecting region defining a first p-n junction in combination with the first semiconductor layer, and a guard ring formed by doping an impurity of the second conductivity type in a surface region of the second semiconductor layer to surround the peripheral portion of the light receiving region with the first semiconductor layer, the second p-n junction having a concentration gradient lower than that of the first p-n junction.Type: GrantFiled: September 27, 1989Date of Patent: February 12, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Hideto Furuyama, Tetsuo Sadamasa
-
Patent number: 4949144Abstract: A semiconductor photo-detector having a two-stepped impurity profile comprises a semiconductor substrate, a light absorption layer of a first conductivity type formed on a semiconductor substrate, a multiplication layer of a first conductivity type formed on the light absorption layer to multiply a photocurrent, a semiconductor region of a second conductivity type formed on the multiplication layer and constituting an abrupt pn junction with the multiplication layer, and a guard ring area of a second conductivity type formed around a periphery of the semiconductor region, whereby the carrier concentration profile of the guard ring region is sharp at its surface and flat below that surface.Type: GrantFiled: September 1, 1988Date of Patent: August 14, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Fumihiko Kuroda, Tetsuo Sadamasa, Nobuo Suzuki, Masaru Nakamura
-
Patent number: 4706101Abstract: A light emitting diode is disclosed which includes an N-GaAs substrate, a double hetero-junction structure obtained by forming an N-GaAlAs clad layer, a P-GaAs active layer and a P-GaAlAs clad layer on the substrate in that order, and a current narrowing structure obtained by selectively forming a contact metal on the P-GaAlAs clad layer in the double hetero-junction structure with the contact metal formed around the contact metal. In the light emitting diode so manufactured, the double hetero-junction structure is formed by a metal organic vapor deposition method. The N-GaAlAs clad layer is of a three-layer structure with one layer of a narrower forbidden band width sandwiched between the remaining two layers of a wider forbidden band width.Type: GrantFiled: August 20, 1985Date of Patent: November 10, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Nakamura, Masaki Okajima, Tadashi Komatsubara, Tetsuo Sadamasa, Koichi Nitta
-
Patent number: 4647927Abstract: A display device having a display array of m.times.n display elements driven by a static shift register having m.times.n stages respectively corresponding to row and column designations of the display elements. The column lines of the display element array are driven by a first output of the m stages. At the same time, pixel data are supplied to the shift register in accordance with a binary level of an externally supplied select signal. Alternatively, the shift register is shifted in a recursive manner. The row lines of the display element array are scanned in accordance with a count of a clock signal. Select signal lines and clock signal lines are respectively aligned along the row and column directions of a unit panel when plural display arrays as described above are arranged in a matrix form to provide a large-screen display unit. The lines of each display array are sequentially driven in accordance with the supply pattern of the select and clock signals from a corresponding unit driver.Type: GrantFiled: December 16, 1985Date of Patent: March 3, 1987Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Osamu Ichikawa, Tetsuo Sadamasa
-
Patent number: 4625223Abstract: A double heterostructure light-emitting semi-conductor device includes a p-GaAs substrate having a first electrode formed on one surface and a current confining layer on the other surface; a confined current conduction layer; and a light-emitting layer structure formed on the current confining layer and the confined current conduction layer. A capping layer of GaAs having a second electrode is formed on the light-emitting layer structure. A light exit window layer for exiting the emitted light is constructed by a thin film of the capping layer.Type: GrantFiled: February 14, 1985Date of Patent: November 25, 1986Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Komatsubara, Tetsuo Sadamasa
-
Patent number: 4465543Abstract: An apparatus transposes a matrix of semiconductor pellets mounted on a first adhesive tape to a second adhesive tape in such a manner that the respective pellet rows are arranged spaced from the adjacent pellet rows. It has pellet-supporting means having an inclined plane and apical plane. The first adhesive tape bearing the matrix is carried stepwise along the inclined plane toward the apical plane to successively bring the respective rows of the matrix to the apical plane. Above the apical plane, a second adhesive tape is carried in a direction intersecting the pellet columns at right angles with the adhesive plane thereof facing the matrix. When each row mounted on the first tape is on the apical plane, the second tape is pressed against the row. Each time one pellet row is transposed to the second tape, the pellet-supporting means is shifted in a direction intersecting the pellet columns at right angles.Type: GrantFiled: September 22, 1982Date of Patent: August 14, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Tetsuo Sadamasa, Osamu Ichikawa, Tatsuro Beppu
-
Patent number: 4445132Abstract: One surface of a substrate of an LED module for a flat panel display has 8.times.8 element areas divided into a matrix form. Row electrodes extend on element areas arranged along the row direction, and column electrodes insulated from the row electrodes extend on element areas arranged in the column direction. At least one LED pellet is disposed for each element area and is connected to the row and column electrode associated with this area. A connecting pad is disposed as spaced apart from the four pellets in a unit area defined as a region consisting of four element areas. This connecting pad is connected to one of the row and column electrodes in the four element areas and is also connected through the substrate to a connecting pin arranged on the other surface of the substrate of the LED module.Type: GrantFiled: June 3, 1981Date of Patent: April 24, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Osamu Ichikawa, Tetsuo Sadamasa
-
Patent number: 4432131Abstract: In a method for manufacturing a display, a substrate having a surface on which a plurality of light-emitting diodes are aligned is disposed such that the surface opposes a surface of a table. A resin of a light-emitting and electrically insulating material which is kept in a fluid state is filled by capillarity into a space defined by the surface of the substrate and the surface of the table. The resin is then hardened, and the table is removed from a hardened resin. A display is obtained wherein at least the space between the adjacent LEDs is filled with the hardened resin.Type: GrantFiled: September 3, 1982Date of Patent: February 21, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Tetsuo Sadamasa, Osamu Ichikawa
-
Patent number: 4322735Abstract: A display device has a relatively large insulation substrate on which a metal layer is formed. On the metal layer on the insulation substrate, there are at least one pair of ceramic unit substrates which are disposed in close vicinity to each other, respectively having thereon metal layers bearing light emitting diodes. The metal layer on the insulation substrate is connected with the metal layers on the unit substrates at its end portions by means of, e.g., flexible lead frames.Type: GrantFiled: May 5, 1980Date of Patent: March 30, 1982Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Tetsuo Sadamasa, Osamu Ichikawa
-
Patent number: 4228455Abstract: A gallium phosphide semiconductor device comprising an N type gallium phosphide monocrystal, a semiconductor layer formed in or on the monocrystal, and a pair of electrodes formed on the monocrystal and on the semiconductor layer. The electrode on the monocrystal is made of a gold-germanium alloy having a predetermined germanium content.Type: GrantFiled: August 29, 1978Date of Patent: October 14, 1980Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Nobuaki Yasuda, Takenobu Ogawa, Tetsuo Sadamasa
-
Patent number: 4145707Abstract: A semiconductor luminescent display apparatus includes a plurality of semiconductor luminescent devices arranged in a row on a header. The device includes a luminescent segments arranged in a letter of eight and electrodes each having a contact surface in contact with one end side of the luminescent surface of the segments in the longitudinal direction thereof.Type: GrantFiled: June 6, 1977Date of Patent: March 20, 1979Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Tetsuo Sadamasa, Makoto Naito, Tadao Nakamura
-
Patent number: 3997907Abstract: A light emitting gallium phosphide device comprising a gallium phosphide (GaP) substrate of one conductivity type and at least one GaP layer of the opposite conductivity type formed on said substrate so as to form a P-N junction, wherein, the GaP layer, when impressed with forward voltage, forms light emitting regions, as viewed from above; and a light absorbing layer prepared from noncrystalline (amorphous) or polycrystalline silicon is mounted on at least one plane selected from the group consisting of the back side of the GaP substrate, those portions of the surface of the GaP substrate on which the GaP layer is not formed and the other portions of the surface of the GaP layer than the light emitting regions thereof, thereby attaining a very favorably acceptable monolithic display in high luminance and distinct contrast.Type: GrantFiled: January 30, 1975Date of Patent: December 14, 1976Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Tadao Nakamura, Tetsuo Sadamasa, Osamu Abe
-
Patent number: 3951699Abstract: A method of manufacturing a gallium phosphide (GaP) red-emitting device by forming at least one n-type GaP layer on an n-type GaP substrate by the liquid phase epitaxial growth process and further depositing a p-type GaP layer on said n-type GaP layer, thereby providing a p-n junction contributing to emission of light, characterized in that the method comprises reducing the surface donor concentration of the n-type GaP layer to below 1 .times. 10.sup.18 cm.sup.-.sup.3 ; and epitaxially growing at least the light emitting region of the p-type GaP layer by cooling a solution for epitaxial growth of said p-type GaP layer at a slower rate than 5.degree.C per minute.Type: GrantFiled: February 6, 1974Date of Patent: April 20, 1976Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Makoto Naito, Akinobu Kasami, Masaru Kawachi, Tetsuo Sadamasa, Hiroki Mineo