Abstract: A communication system using a network route establishing technique for a network having a plurality of nodes connected through links, in which a route search message is delivered simultaneously in a plurality of directions from a sender node through a network route to a destination node, and a confirmation is delivered from the destination through the network route back to the sender node, and accordingly, a network route is established. The communication system includes a device for detecting, at a node through which a search message is to be transmitted, a possibility of a transmission of the search message beyond the node, a device for delivering a cancel message in the direction from which the search message has been transmitted, and a device for releasing the network route engaged by the search message, based on the delivered cancel message.

Abstract: A method for structuring a communications network based on an asynchronous transfer mode in which communications are held with the use of cells transferred between a node on the upstream side and a node on the downstream side. The method for structuring the network includes a step for preparing a plurality of VPI conversion tables for converting VPIs of the cell input under normal communicating conditions and that of the cell input in the event of a failure and outputting the cell with the VPI converted. The prepared VPI conversion tables are reorganized for each node and the reorganized VPI conversion tables are distributed to all nodes. Then, an alternate route monitoring and switching virtual path is set up in each alternate route and a monitoring cell is periodically transmitted along the alternate route.

Abstract: A route switching system in a communications network constituted of a transmitter and a receiver connected by a plurality of routes for switching a first route along which communication is being held by transmission of cells to a second route causing no blocking. The route switching system comprises a first switch provided in the transmitter for switching input cells from one route to another and outputting the cells, a first storage portion provided in the transmitter for storing the input cells, a second switch provided in the receiver for switching input cells from one route to another and outputting the cells, and a second storage portion provided in the receiver for storing the input cells. At the time when the route is switched over, the first switch is changed over so that the cells are transmitted through the first storage portion and, on the receiver side, the second switch is changed over so that the cells transmitted over the second route are stored into the second storage portion.

Abstract: A method includes the steps of a failure which occurs in a node or link, and b) identifying at most N (N is an integer equal to or greater than 2) nodes contained in each path affected by the occurrence of the failure. Each path is connected to a sender node which detects the failure, information is transferred to the sender node via the N nodes, and the sender node serves as a start point of each alternate path which is to be established. The method also includes the step of c) broadcasting a restoration message to links which outgo from the sender node, where the restoration message has an identifier of the sender node and identifiers of the N nodes specified for each path affected by the occurrence of the failure. The identifiers of the N nodes specified for each path being candidate nodes of an end point of each alternate path.

Abstract: A communication system containing a master station and a plurality of slave stations. The master station receives a request from one of the plurality of slave stations and memorizes one or more requests from one or more slave stations. The master station also sends a request sending allowance signal which addresses one of the plurality of slave stations to give an allowance to send a request for sending data, and sends a data sending allowance signal which addresses one of the plurality of slave stations to give an allowance to send data, according to a request which is memorized. Each of the slave stations detects a request sending allowance signal which addresses its own slave station, and a data sending allowance signal which addresses its own slave station. Each of the slave stations also sends a request for sending data to the master station when its own slave station detects a request sending allowance signal which addresses its own slave station.

Abstract: A communication system including a master station, a plurality of slave stations each for communicating with the master station, a two-way transmission line connecting the master station and the plurality of slave stations. Each of the slave stations sends a request for further communication with the master station, to the master station when its own slave station is allowed to communicate with the master station and its own slave station has the above request. The master station detects the request for further communication with the master station in a signal sent from a slave station, and memorizes the slave station from which the request for further communication with the master station is detected, until an allowance signal is sent to the slave station from the master station corresponding to the memorizing of the slave station.

Abstract: A coded transmission system wherein each bit of transmitted data having a logical value is coded depending on a coded result of a preceding bit. The coded transmission system contains a sender-side apparatus, a transmission line, and a receiver-side apparatus. In the sender-side apparatus, a resetting bit and a message are generated; a code of a bit last transmitted which is necessary to code a bit which is to be transmitted next is memorized in a first preceding code memorizing circuit; and the content of the first preceding code memorizing circuit is reset to an initial code responding to the resetting bit. A coding circuit receives the resetting bit and the message, codes each bit of the message in accordance with a predetermined coding rule and the content of the first preceding code memorizing circuit, and codes the resetting bit to a predetermined resetting code which is different from the codes used in the coding of the message.

Abstract: A frame synchronization method in which a synchronization detection of a frame synchronization signal using one of n-multiplexed frame synchronization signals derived from a sequence of frame synchronization signals each delayed by one bit from the preceding frame synchronization signal, a synchronization confirmation as synchronization guard by detecting a repetition of the synchronization detections of the frame synchronization signal, a confirmation of the subsequent frame identification signal based on the synchronization confirmation; and a separation of the received multiplexed signals into a plurality of channels based on the synchronization confirmed frame synchronization signal and the confirmed frame identification signal are carried out.

Abstract: A circuit which operates at the fixed timing and discriminates the control signal is provided and the timing pulse for demultiplexing is controlled in accordance with the discriminated control signal in the receiving part of the synchronized multiplexing system in which the basic signals are generated by inserting the control signal required for multiplexing on the frame structure of basic signal rate and the high level multiplexing signal is formed by multiplexing such basic signals, thereby stable correspondence between the channel at the time of multiplexing in the sending side and the channel after the demultiplexing in the receiving side can be ensured.

Abstract: A programmable multiplexing/demultiplexing system used in a digital communication network, suitable for an ISDN to be developed. The system including a phase adjusting unit, a bit length varying unit, a start timing control unit, and a processor which variably controls the three units. The phase adjusting unit variably controls the phase of an internal clock in accordance with received data, and the thus-adjusted clock is used by the remaining two units. The bit length varying unit variably controls the bit length of the received data. The start timing control variably controls the start timing of each transmission and reception processing carried out alternately by the processor.

Abstract: In a sequential polling type communication network system including a master station, a first channel, a second channel, and at least two slave stations, the master station includes request registration units for registering data transmission requests from slave stations during a data transmission by another slave station, and an interrupt polling unit for polling the slave station which has issued the data transmission request after completion of the data transmission or completion of a polling of a slave station, and the slave station includes a unit for responding to a polling during the data transmission, and transitting a data transmission request when data to be transmitted exists, and for responding to the interrupt polling from the master station, and transmitting the data to the master station until the data transmission is completed.

Abstract: Disclosed is a frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication. The digital signals consists serial signals at a rate of f.sub.0 (bps). The serial signals include a frame synchronizing signal consituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame. To attain a high-speed operation and a shorter synchronization establishing time, the apparatus comprises a latching circuit for converting the serial signals into parallel signals and for latching the parallel signals, and a circuit for detecting a plural number of times of synchronization during the n bit interval in one frame.

Abstract: A demultiplexing circuit includes a frame synchronization circuit which simultaneously detects the occurrence of a predetermined frame synchronization pattern and the occurrence of a predetermined identification byte within the frame synchronization pattern. Since the pattern and identification bit are detected simultaneously and from the same data, the circuit is simplified and the demultiplexing is performed more quickly and efficiently.

Abstract: An optical bus type communication system comprises a bus type transmission line consisting of an optical fiber, a light source provided at the one end of the bus type transmission line for sending an optical signal having a constant level to the bus type transmission line, a plurality of optical switches mounted on the bus type transmission line, and a plurality of terminal interfaces. Each terminal interface sends data by switching the corresponding optical switch so that the optical signals on the transmission line are modulated with the data.

Abstract: A multiplexing apparatus of a bit interleave type for time-division multiplex on PCM signals of a plurality of channels bit by bit to convert the PCM signals into a high-speed PCM signal. To maintain the advantage of the synchronous multiplex system, the multiplexing apparatus has a BSI-code processing function and a bit interleave function and comprises: a BSI-code adding circuit for adding BSI codes to the PCM signals before multiplexing; a BSI-code position shifting means circuit for shifting the positions of the BSI codes in the PCM signals to different positions respectively with respect to the PCM signals of a plurality of channels; and a multiplexing circuit for multiplexing the outputs of the BSI-code position shifting circuit by a bit-interleave mode.

Abstract: An information communication system having a plurality of terminal equipment units, a network termination unit, a receive (R) line, and transmit (T) line. The terminal equipment units are commonly connected to the R and T line so as to communicate with the network termination unit. The communication is achieved in the form of successive frame signals, each composed of at least successive channels. Each terminal equipment determines a delay time for channel insertion into the frame signal on the T line. the delay time is determined during a learning identification algorithm operation which takes the transmission delay time along the R and T lines into consideration.

Abstract: A shift register circuit for converting a form of a datum with N bits comprises a shift register with a bit capacity of at least N+1 bits. Each bit of the shift register is set so as to become a predetermined logic condition by a setting means. At this time, the supply of shift pulses to the shift register is begun, so that the data in the shift register is shifted and predetermined data are input in sequence. A detecting means detects whether or not the shift register has carried out the shift operations by the predetermined times on the basis of the logical condition of the predetermined bit or bits in the shift register. When the detecting means detects that the shift operations have been carried out by the predetermined times, the supply of the shift pulses to the shift register is stopped. This shift register circuit can be used for a parallel to serial converter or a serial to parallel converter.