Patents by Inventor Tetsuo Takeshita

Tetsuo Takeshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4478680
    Abstract: A method for treating an electrolytic diaphragm formed by adhering asbestos fibers to the surface of an electrolytic cathode made of a wire mesh or porous plate, which comprises permeating water glass into the diaphragm, then permeating a chloroprene latex into the water glass-treated diaphragm, and drying the treated diaphragm under heat.
    Type: Grant
    Filed: March 2, 1983
    Date of Patent: October 23, 1984
    Assignee: Showa Denko K.K.
    Inventors: Takeshi Adachi, Tetsuo Takeshita, Itsuaki Matsuda
  • Patent number: 4385336
    Abstract: This invention relates to a current supplying circuit for supplying a current to a terminal apparatus through a ring line and a tip line which are connected through resistance elements to a potential source and ground, respectively. This current supplying circuit includes respective detectors for generating first and second detection signals of amplitudes proportional to the currents flowing in the ring and tip lines, respectively, a circuit for generating a reference signal, and a comparator for comparing the signal difference between the first and second detection signals and the reference signal so as to produce a signal in accordance with the compared result, thus a shorted-to-ground fault on the ring line or tip line being detected by monitoring the signal produced in accordance with the compared result. After the shorted-to-ground fault is detected, the current supplying circuit is protected from breakdown.
    Type: Grant
    Filed: December 4, 1980
    Date of Patent: May 24, 1983
    Assignees: Hitachi, Ltd., Nippon Telegraph & Telephone Public Corporation
    Inventors: Tetsuo Takeshita, Junjiro Kitano, Koichi Hagishima
  • Patent number: 4360709
    Abstract: A circuit for detecting a closed loop formed by actuation of a telephone set, the loop being indicative of a connection between the telephone set and an exchange through a ring line and a tip line. The detecting circuit comprises generators for generating first and second detection signals having amplitudes proportional to a ring line current and a tip line current respectively, a summing circuit for summing the detection signals and a comparator for comparing the outputs of the summing circuit and a reference value and delivering an output depending upon the result of comparison.
    Type: Grant
    Filed: September 4, 1980
    Date of Patent: November 23, 1982
    Assignees: Hitachi, Ltd., Nippon Telegraph & Telephone Public Corporation
    Inventors: Kazuo Hamazato, Junjiro Kitano, Tetsuo Takeshita
  • Patent number: 4264895
    Abstract: A multi-stage switching network comprises a plurality of unitary switch matrices each including a number of cross-point circuits each of which in turn includes a memory circuit operatively connected to the associated cross-point switches in a speech path. The plurality of the unitary switch matrices are arranged in a matrix array in which each stage of the multi-stage switching network is constituted by the unitary switch matrices arrayed in at least one column thereof and interconnected through links.
    Type: Grant
    Filed: March 2, 1979
    Date of Patent: April 28, 1981
    Assignees: Nippon Telegraph and Telephone Public Corp., Hitachi, Ltd.
    Inventors: Takuji Mukaemachi, Tetsuo Takeshita, Keiichi Shimizu, Ryoichi Himeno
  • Patent number: 4170536
    Abstract: A novel cathode for use in electrolysis of an aqueous solution of an alkali metal halide or water is provided which comprises a metallic cathode substrate and a powder of Raney nickel held on its surface partly embedded in a nickel layer deposited thereon from a nickel plating bath. The cathode has a considerably lower hydrogen overvoltage than ordinary cathodes. It can be produced by electrolytically depositing nickel on the surface of a metallic cathode substrate from an aqueous nickel plating bath containing a powder of Raney nickel suspended therein to form a co-deposited layer of the nickel and the Raney nickel powder.
    Type: Grant
    Filed: November 13, 1978
    Date of Patent: October 9, 1979
    Assignee: Showa Denko K.K.
    Inventors: Keiji Kawasaki, Tetsuo Takeshita
  • Patent number: 4113988
    Abstract: A speech path apparatus in a space-division type electronic exchanger equipment wherein a plurality of switching networks each having controlled points and a plurality of trunks are divided into an appropriate number of packaging units, and a network controller and a trunk controller are provided for each packaging unit. Each of the network controllers and the trunk controllers includes a shift register for receiving a control signal sent from a central processing unit in serial form, a means for determining whether the received control signal is for its own unit and means for translating a control signal stored in the shift register to send it out in parallel form to the controlled point.
    Type: Grant
    Filed: March 8, 1977
    Date of Patent: September 12, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Takuji Mukaemachi, Tetsuo Takeshita, Shiroh Enami
  • Patent number: 4075431
    Abstract: A speech path system for a telephone exchange having crosspoint switches of a speech path network comprising semiconductor switching devices of four or more layers, including a memory circuit for storing the operating conditions of said switching devices, a drive circuit of a high A.C. impedance for actuating said switching devices in response to output signals from said memory circuit, a subscriber D.C. loop detection circuit of a high impedance provided at a subscriber terminal of said speech path network, and a speech current supply circuit with speech current switching means and a supply current detection circuit provided at a trunk terminal of said speech path network.
    Type: Grant
    Filed: February 26, 1976
    Date of Patent: February 21, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Takuji Mukaemachi, Tetsuo Takeshita, Tatsuru Miyoshi, Takafumi Kojima
  • Patent number: 4031413
    Abstract: A memory circuit for providing a zero OFF-holding power under the logical control of three inputs comprises a memory cell including a semiconductor element circuit of equivalently four PNPN layer structure and a logical input section including at least one PNP transistor and NPN transistor with the collector of the PNP transistor connected to the base of the NPN transistor. The NPN transistor in the logical input section has its collector connected to the control gate of the memory cell, and logical input signals are applied to the emitter and base of the PNP transistor and the emitter of the NPN transistor in the logical input section, respectively.
    Type: Grant
    Filed: January 2, 1976
    Date of Patent: June 21, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Ohhinata, Shinzi Okuhara, Tetsuo Takeshita