Patents by Inventor Tetsuo Tateyama

Tetsuo Tateyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Optical receiving device, waveform optimization method for optical data signals, and waveform optimization program for optical data signals
    Patent number: 7123846
    Abstract: This optical receiving device for discriminating and recovering a data signal, which results from converting an optical signal input through a dispersion equalizer into an electrical signal and amplifying it to a pre-determined amplitude, by using a clock and data recovery circuit for discriminating a data signal at the decision point controlled to achieve the optimum position controls the dispersion characteristics of a dispersion equalizer so that the error count in the recovered data signal by using a clock and data recovery circuit will be minimized by controlling the eye pattern of the data signal which has been amplified to a pre-determined amplitude.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: October 17, 2006
    Assignee: NEC Corporation
    Inventors: Tetsuo Tateyama, Takashi Kuriyama, Yoshihiro Matsumoto
  • Optical receiving device, waveform optimization method for optical data signals, and waveform optimization program for optical data signals
    Publication number: 20030016605
    Abstract: This optical receiving device for discriminating and recovering a data signal, which results from converting an optical signal input through a dispersion equalizer into an electrical signal and amplifying it to a pre-determined amplitude, by using a clock and data recovery circuit for discriminating a data signal at the decision point controlled to achieve the optimum position controls the dispersion characteristics of a dispersion equalizer so that the error count in the recovered data signal by using a clock and data recovery circuit will be minimized by controlling the eye pattern of the data signal which has been amplified to a pre-determined amplitude.
    Type: Application
    Filed: July 17, 2002
    Publication date: January 23, 2003
    Applicant: NEC Corporation
    Inventors: Tetsuo Tateyama, Takashi Kuriyama, Yoshihiro Matsumoto
  • Phase detection circuit
    Patent number: 6377081
    Abstract: The detection circuit comprising: a first D-type flip-flop circuit F/F1, to which the data signal D1 and the clock signal C1 are input; a first delay circuit DL2 which delays the clock signal C1 by a prescribed amount of time, so as to generate a delayed clock signal C1′; a second D-type flip-flop circuit F/F2, to which the output signal Q1 of the first D-type flip-flop circuit F/F1 and the delayed clock signal C1′ are input; a second delay circuit DL1 which delays the an output signal Q2 of the second D-type flip-flop circuit F/F2 so as to generate a first delayed signal Q2′, a third delay circuit DL3 which delay the an output signal Q1 of the first D-type flip-flop circuit F/F1 so as to generate a second delayed signal Q1′, a fourth delay circuit DL4 which delays the data signal D1 so as to generate a delayed data signal D1′, a first AND circuit AND2 which calculates a logical product of the first delayed signal Q2′ and the second delayed signal Q1′ so as to output
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: April 23, 2002
    Assignee: NEC Corporation
    Inventor: Tetsuo Tateyama