Abstract: A semiconductor device structure includes a region of semiconductor material comprising a first conductivity type, an active region, and a termination region. A first active trench structure is disposed in the active region, and a second active trench structure is disposed in the active region and laterally separated from the first active trench by an active mesa region having a first width. A first termination trench structure is disposed in the termination region and separated from the second active trench by a transition mesa region having a second width and a higher carrier charge than that of the active mesa region. In one example, the second width is greater than the first width to provide the higher carrier charge. In another example, the dopant concentration in the transition mesa region is higher than that in the active mesa region to provide the higher carrier charge.

Abstract: A semiconductor device structure includes a region of semiconductor material comprising a first conductivity type, an active region, and a termination region. A first active trench structure is disposed in the active region, and a second active trench structure is disposed in the active region and laterally separated from the first active trench by an active mesa region having a first width. A first termination trench structure is disposed in the termination region and separated from the second active trench by a transition mesa region having a second width and a higher carrier charge than that of the active mesa region. In one example, the second width is greater than the first width to provide the higher carrier charge. In another example, the dopant concentration in the transition mesa region is higher than that in the active mesa region to provide the higher carrier charge.

Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

Abstract: A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially eliminates the possibility of the high-frequency analog signal transmitting to the control terminal pad. Accordingly, an increase in insertion loss can be suppressed.

Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

Abstract: A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.

Abstract: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.

Abstract: High-resistance elements are connected as parts of a control resistor between a switching element and a protecting element immediately near the switching element and between adjacent protecting elements. Paths for high-frequency signals are cut off, and high-frequency signals can be prevented from leaking although there are parasitic capacitances due to the protecting elements being connected. Accordingly, electrostatic breakdown voltage can be improved, and isolation can be prevented from deteriorating.

Abstract: A unit HBT and a unit FET are arranged to be adjacent to each other through an isolation region and a base electrode of the unit HBT is connected to a source electrode of the unit FET to form a unit element, and a plurality of unit elements are connected to form an active element. This makes it possible to implement the active element in which a current is not likely to concentrate on the unit element and no destruction is generated by the second breakdown. Moreover, although a buried gate electrode structure is used to ensure a withstand pressure in the unit FET, a buried portion is structured not to be diffused to an InGaP layer, and thereby it is possible to prevent Pt from being abnormally diffused. Furthermore, a selection etching can be used for a formation of an emitter mesa, that of a base mesa, that of a ledge in the unit HBT, and a gate recess etching in the unit FET, and a good reproducibility can be obtained.

Abstract: A gate wiring electrode is formed into a ladder-like pattern. Moreover, between source electrodes and drain electrodes in the entire Switch MMIC, the gate wiring electrodes are disposed. Furthermore, at a cross part between the gate wiring electrode and the source electrode or the drain electrode, a nitride film having a large relative dielectric constant and a polyimide or a hollow part having a small relative dielectric constant are disposed. Accordingly, a capacitance at the cross part is reduced. Thus, a second harmonic wave level can be lowered. Moreover, a leak of a high-frequency signal between the drain electrode and the source electrode can be prevented. Thus, a third harmonic level can be lowered. Consequently, distortion characteristics of the Switch MMIC can be significantly improved.

Abstract: Protecting elements are respectively connected between a control terminal Ctl and a ground terminal GND of a logic circuit L, between a point Cp and a ground terminal GND, and between a power supply terminal VDD and a ground terminal GND thereof. With this, an E-FET, constituting an inverter 70, and capacitors Ci and Cr can be protected from electrostatic breakdown due to external static electricity. Since the protecting element can be constituted by requisite components for the logic circuit, an additional step or structure is not especially required to provide the protecting element.

Abstract: High resistance elements of 5 K? or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second connectings, the high frequency analog signal is attenuated by the high resistance elements. Accordingly, the high frequency analog signal is not substantially transmitted to control terminal pads. It is therefore possible to suppress an increase in insertion loss.

Abstract: A pad electrode of a field effect transistor is formed solely of a pad metal layer without providing a gate metal layer. A high concentration impurity region is provided below the pad electrode, and the pad electrode is directly contacted to a substrate. Predetermined isolation is ensured by the high concentration impurity region. Accordingly, in a structure not requiring a nitride film as similar to the related art, it is possible to avoid defects upon wire boding attributing to hardening of the gate metal layer. Therefore, in the case of a buried gate electrode structure for enhancing characteristics of the field effect transistor, it is possible to enhance reliability and yields.

Abstract: With a microwave FET, the internalized Schottky junction capacitance or pn junction capacitance is small and these junctions are weak against static electricity. However, with a microwave device, a protecting diode could not be connected since the increase of parasitic capacitance resulting from this method causes degradation of the high frequency characteristics. Therefore, to eliminate this problem, a semiconductor device is provided, wherein two paths, extending from a gate electrode pad to a gate electrode on an operating region, are arranged, with one path running near a source electrode pad, the other path running near a drain electrode pad, and at the respective parts where a path becomes close to a pad, the abovementioned protecting elements are connected between the gate electrode and source electrode and between the gate electrode and drain electrode to improve the electrostatic breakdown voltage of the FET from approximately 100V to 700V.

Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. The gate width of each FET is about 400 ?m, and the maximum power required for the device operation is maintained by a lager conductivity of the channel layer of one FET and by a lower conductivity of the channel layer of another FET. The device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

Abstract: An island-shaped floating conducting region is provided in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, or peripheral impurity region), or between the adjacent wire on the nitride film and gate metal layer. The floating conducting region has floating potential and blocks a depletion layer extending from the wire on the nitride film to the substrate. It is therefore possible to prevent leakage of a high frequency signal to the other side through the depletion layer extending from the wire on the substrate to the substrate in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, peripheral impurity region), or between the adjacent wire on the nitride film and gate metal layer.

Abstract: Floating conducting regions at floating potentials are placed on a substrate surface between adjacent conducting regions to which predetermined potentials are applied. This makes it possible to block the spread of a depletion layer to the substrate between the conducting impurity regions. Thus, the leakage of high-frequency signals can be suppressed. In particular, in a case where a floating conducting region is placed between a peripheral impurity region of a common input terminal pad and a resistor in a switch circuit device, it is possible to suppress the leakage of high-frequency signals from an input terminal to control terminals which become high frequency GND and to suppress an increase in insertion loss.

Abstract: Between a terminal of an element to be protected and a GND terminal, a protecting element is connected, which includes a first n+ region, an insulating region and a second n+ region. The first n+ region is provided to have a columnar shape in a depth direction of a substrate, and the second n+ region is formed to have a plate shape and disposed so as to face a bottom of the first n+ region. Thus, it is possible to allow a very large static current to flow into a ground potential through a first current path and a second current path. Thus, electrostatic energy reaching an operation region of a HEMT can be significantly reduced while hardly increasing a parasitic capacity.