Patents by Inventor Tetsuro Hirano

Tetsuro Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137128
    Abstract: An optical transmission system including an optical transmission device and an optical reception device that receives, via an optical transmission line, a signal transmitted from the optical transmission device, the optical transmission system including a transmission-mode selection unit that selects transmission mode information in descending order of priority out of transmission mode information, which is combinations of a plurality of parameters concerning transmission performance, the transmission mode information being a plurality of kinds of the transmission mode information common to the transmission performance of the optical transmission device and the optical reception device, a signal transmission unit that transmits, to the optical reception device, a signal modulated based on the selected transmission mode information, and a signal reception unit that receives the signal and modulates the received signal based on the transmission mode information selected by the transmission-mode selection unit.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 25, 2024
    Inventors: Tetsuro Inui, Hideki Nishizawa, Seiji Okamoto, Akira Hirano, Shokei Kobayashi, Fumikazu Inuzuka, Seiki Kuwabara, Takafumi Tanaka, Kei Kitamura, Takuya Oda
  • Patent number: 9136717
    Abstract: A circuit device connected between a neighboring pair of terminals in a semiconductor integrated circuit is protected from electrostatic damage due to a surge voltage when the surge voltage is applied between the neighboring pair of terminals. The semiconductor integrated circuit is formed to include terminals P0-P14, MOS transistors MN0-MN15 in diode connection, protection diode circuits HD0-HD14, MOS transistors T1-T14 for discharging electricity from batteries, a battery voltage detection control circuit and a clamp circuit for overvoltage protection. Each of the MOS transistors T1-T14 for discharging electricity from the batteries is connected between each neighboring pair of the terminals P0-P14 through wirings. Each of the MOS transistors MN1-MN14 in diode connection is connected between each neighboring pair of the terminals.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 15, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kyouichi Kashima, Yoshitaka Fukushima, Masahiro Ono, Tetsuro Hirano
  • Patent number: 8723258
    Abstract: An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Kiyofumi Nakaya, Tetsuro Hirano, Shuji Fujiwara
  • Publication number: 20120061757
    Abstract: An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 15, 2012
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Kiyofumi NAKAYA, Tetsuro HIRANO, Shuji FUJIWARA
  • Publication number: 20110235224
    Abstract: A circuit device connected between a neighboring pair of terminals in a semiconductor integrated circuit is protected from electrostatic damage due to a surge voltage when the surge voltage is applied between the neighboring pair of terminals. The semiconductor integrated circuit is formed to include terminals P0-P14, MOS transistors MN0-MN15 in diode connection, protection diode circuits HD0-HD14, MOS transistors T1-T14 for discharging electricity from batteries, a battery voltage detection control circuit and a clamp circuit for overvoltage protection. Each of the MOS transistors T1-T14 for discharging electricity from the batteries is connected between each neighboring pair of the terminals P0-P14 through wirings. Each of the MOS transistors MN1-MN14 in diode connection is connected between each neighboring pair of the terminals.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 29, 2011
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Kyouichi KASHIMA, Yoshitaka Fukushima, Masahiro Ono, Tetsuro Hirano