Abstract: A data processing system includes a plurality of computers which include a processor and a memory, a storage device which is connected to the plurality of computers to store data, and a management computer controls the plurality of computers. The computer includes a node pool which can perform, stop, and delete one or more nodes. The node pool includes one or more first nodes which function as a data buffer. The management computer causes the node to measure a performance of data transmission between the data buffer and the storage device, determines a number of increased/decreased nodes on the basis of a measurement result of the performance, and notifies the node pool of a command of performing or deleting the first node according to the determined number of increased/decreased nodes. The node pool adjusts a number of the first nodes according to performing or deleting command.

Abstract: This computer system includes: at least one computer having a memory and a plurality of CPU cores; and a storage sub device having a plurality of logical storage units configured using storage devices. In the computer, a plurality of queues are configured in the memory, and at least one of the plurality of CPU cores is assigned to each of the plurality of queues. The queue is enqueued with an I/O command dispatched from a CPU core, to which the queue is assigned, to a logical storage unit. The computer system has access control information including information concerning whether to accept or refuse access from each queue to each logical storage unit.

Abstract: A data processing system includes a plurality of computers which include a processor and a memory, a storage device which is connected to the plurality of computers to store data, and a management computer controls the plurality of computers. The computer includes a node pool which can perform, stop, and delete one or more nodes. The node pool includes one or more first nodes which function as a data buffer. The management computer causes the node to measure a performance of data transmission between the data buffer and the storage device, determines a number of increased/decreased nodes on the basis of a measurement result of the performance, and notifies the node pool of a command of performing or deleting the first node according to the determined number of increased/decreased nodes. The node pool adjusts a number of the first nodes according to performing or deleting command.

Abstract: A computer system according to one preferred embodiment of the present invention has a server and a storage subsystem, wherein the server is configured to enable data write to a cache area of the storage subsystem. Further, the server manages the usages of the cache area. When storing data from the server to the cache area, the server determines whether a data-writable area exists in the cache area or not. If there is a writable area, data is stored in the writable area.

Abstract: This computer system includes: at least one computer having a memory and a plurality of CPU cores; and a storage sub device having a plurality of logical storage units configured using storage devices. In the computer, a plurality of queues are configured in the memory, and at least one of the plurality of CPU cores is assigned to each of the plurality of queues. The queue is enqueued with an I/O command dispatched from a CPU core, to which the queue is assigned, to a logical storage unit. The computer system has access control information including information concerning whether to accept or refuse access from each queue to each logical storage unit.

Abstract: A computer system according to one preferred embodiment of the present invention has a server and a storage subsystem, wherein the server is configured to enable data write to a cache area of the storage subsystem. Further, the server manages the usages of the cache area. When storing data from the server to the cache area, the server determines whether a data-writable area exists in the cache area or not. If there is a writable area, data is stored in the writable area.

Abstract: A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

Abstract: A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

Abstract: A semiconductor integrated circuit device which guarantees the characteristics of writing to and reading from the built-in memory even when the manufacturing process conditions are varied, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, an output register, a register controlled by a register control a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.

Abstract: A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

Abstract: A semiconductor integrated circuit device supplied as an IP (Intellectual Property), etc., a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing, more particularly to a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied.

Abstract: A semiconductor integrated circuit device supplied as an IP (Intellectual Property), etc., a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing, more particularly to a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.

Abstract: A semiconductor integrated circuit device supplied as an IP (Intellectual Property), etc., a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing, more particularly to a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied. pa The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.

Abstract: A semiconductor integrated circuit device, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing are disclosed. More particularly, a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied is obtained. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by the BIST, thereby deciding the optimal timing.

Abstract: An address translation apparatus which includes a memory for storing a plurality of physical addresses, and a content addressable memory unit which stores a plurality of signal pairs that correspond to the plurality of physical addresses, each of the signal paris includes a logical address that corresponds to one of the plurality of physical addresses and memory protection level data that indicates a memory protection level allocated to a memory position of the one of the physical addresses. The content addressable memory unit includes apparatus for searching a signal pair that has a logical address in coincident with a logical address being subjected to address translation and comparing memory protection level data to comparative data at a bit position which is indicated to be the bit position to be searched by mask data, in response to the logical address translation.