Patents by Inventor Tetsuro Iwashita

Tetsuro Iwashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8877643
    Abstract: This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. The method of polishing a silicon wafer by supplying a polishing solution containing abrasive grains onto a surface of a polishing pad and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, is characterized in that the number of abrasive grains included in the polishing solution is controlled to not more than 5×1013 grains/cm3.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 4, 2014
    Assignee: Sumco Corporation
    Inventors: Shuhei Matsuda, Tetsuro Iwashita, Ryuichi Tanimoto, Takeru Takushima, Takeo Katoh
  • Patent number: 8815710
    Abstract: Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode).
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: August 26, 2014
    Assignee: Sumco Corporation
    Inventors: Masayuki Ishibashi, Shinji Nakahara, Tetsuro Iwashita
  • Publication number: 20120080775
    Abstract: This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. The method of polishing a silicon wafer by supplying a polishing solution containing abrasive grains onto a surface of a polishing pad and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, is characterized in that the number of abrasive grains included in the polishing solution is controlled to not more than 5×1013 grains/cm3.
    Type: Application
    Filed: May 28, 2010
    Publication date: April 5, 2012
    Inventors: Shuhei Matsuda, Tetsuro Iwashita, Ryuichi Tanimoto, Takeru Takushima, Takeo Katoh
  • Publication number: 20110031592
    Abstract: Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode).
    Type: Application
    Filed: April 17, 2009
    Publication date: February 10, 2011
    Applicant: SUMCO CORPORATION
    Inventors: Masayuki Ishibashi, Shinji Nakahara, Tetsuro Iwashita
  • Patent number: 7479204
    Abstract: A method of evaluating the presence or absence and/or degree of metal contamination of a semiconductor substrate including etching the surface of the semiconductor substrate by SC-1 cleaning and/or a HF cleaning, detecting bright points on the surface of the etched substrate with a foreign matter inspection device, and evaluating the presence or absence and/or degree of metal contamination of the semiconductor substrate based on the distribution pattern of bright points detected on the surface of the substrate. Also disclosed is a method of manufacturing a semiconductor substrate comprising mirror polishing a silicon wafer surface, wherein the mirror polishing is conducted using a slurry having a Cu content of approximately equal to or less than 10 ppb, a Ni content of approximately equal to or less than 10 ppb, and an Fe content of approximately equal to or less than 1,000 ppb, and evaluating the semiconductor substrate as above.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: January 20, 2009
    Assignee: Sumco Corporation
    Inventors: Morimasa Miyazaki, Takafumi Kitamura, Tetsuro Iwashita, Mihoko Ohira
  • Publication number: 20070193686
    Abstract: The method of manufacturing a semiconductor substrate including mirror polishing a silicon wafer surface, wherein the mirror polishing is conducted using a slurry having a Cu content of approximately equal to or less than 10 ppb, a Ni content of approximately equal to or less than 10 ppb, and an Fe content of approximately equal to or less than 1,000 ppb. The method of evaluating a quality of a semiconductor substrate including etching the surface of the semiconductor substrate by SC-1 cleaning and/or a HF cleaning, detecting bright points on the surface of the etched substrate with a foreign matter inspection device, and evaluating the quality of the semiconductor substrate based on the bright points detected on the surface of the substrate.
    Type: Application
    Filed: November 29, 2006
    Publication date: August 23, 2007
    Applicant: SUMCO CORPORATION
    Inventors: Morimasa MIYAZAKI, Takafumi KITAMURA, Tetsuro IWASHITA, Mihoko OHIRA