Abstract: The integrated drawing processor handles the image data that cannot be processed at a required rate by transferring the image data to a non-real-time path unit from an operation processor through an operation processor interface, where the data is processed. Thereafter, the data is transferred through the operation processor interface to the address of a designated storage unit. The transferred data is processed by the operation processor interface necessary, or repeatedly processed by the non-real-time path unit, or transferred to the real-time path unit, and fmally transferred to an output device. The image data that can be processed at the required rate is transferred directly to the real-time path unit through the operation processor interface. The image data transferred to the real-time path unit is outputted to the output device through an output device interface.

Abstract: A print processing apparatus realizes high speed processing of input data which includes various types of drawing objects such as images, graphics and characters. In the apparatus, input data generated by an input data generating unit is converted into intermediate data in an intermediate data generating element. An intermediate data order controlling element rearranges intermediate data pieces based on overlap therebetween and classifies them into groups, in each of which the data pieces can be processed in parallel. A group ID indicating a group for parallel processing, a hardware configuration ID and so on are assigned to the intermediate data piece. A rasterizing unit receives configuration data from a configuration data administering element, if necessary, in accordance with the hardware configuration ID assigned to the intermediate data piece, and rewrites a function of a reconfigurable rasterizing element under the control of the reconfiguration controlling element.

Abstract: A print processor is disclosed which comprises: an input unit for inputting print data including at least either texts or graphics and described in predetermined drawing instructions; an image output unit for outputting images based on data having a predetermined data structure; an intermediate data generating unit for generating intermediate data from the print data, the intermediate data being expressed in a format which is higher in abstract terms than the data structure and which includes at least one basic graphic; an rasterizing process unit for rasterizing the intermediate data into the data structure and for supplying the image output unit with the intermediate data thus rasterized; a determining unit for determining a number and a size of the basic graphics constituting the intermediate data generated by the intermediate data generating unit; an rasterizing time predicting unit for predicting the time it takes the rasterizing process unit to rasterize the intermediate data on the basis of the number

Abstract: A ring bus multiprocessor system whose processors are laid out and connected in such a manner that the system is enhanced in stability and performance, is easy to modify in scale, and is lowered in manufacturing cost. On a processor board, processors are serially connected by communication buses to form a processor group. Each processor board may have an even-numbered plurality of processor groups mounted thereon. A plurality of processor boards are laid out in parallel and are interconnected between adjacent boards by means of inter-processor communication buses. Each of the odd-numbered processor groups is connected from one board to the next up to the most downstream board where the connection is looped back to the adjacent even-numbered processor group. In turn, the even-numbered processor group is connected from one board to the next back to the most upstream board where the connection is again looped back to the adjacent odd-numbered processor group, and so on, whereby a ring bus arrangement is formed.

Abstract: A field-programmable gate array comprises regularly arrayed logic elements, a first group of signal lines interconnecting the logic elements adjacent to each other, and a second group of signal lines interconnecting the logic elements not adjacent to each other to provide a field-programmable gate array capable of forming an adder, logic operation unit, or the like having a high utilization of logic elements.

Abstract: A decoder used for graphic processing or the like. The decoder includes a first input unit for inputting coordinates of two points, a second input unit for inputting a direction between the two points, and an operation unit for logically operating a relationship between the two points utilizing a symmetry of coordinates on the basis of data supplied from the first and second input units. According to the decoder, the scale of the circuit can be reduced.

Abstract: A hierarchical circuit data base optimizing apparatus and a hierarchical circuit data base optimizing method which select and put out a specific partial circuit from a hierarchical circuit data base, compare the number of the interface signals found to be present between this partial circuit and the circuit module at the particular hierarchical level with the number of the interface signals found to be present between this partial circuit and another circuit module at the same hierarchical level, and renews the hierarchical structure of the circuit data base in case the latter number of the interface signals is smaller than the former number.

Abstract: In a digital data processor having a CPU, a condition instruction is fetched from memory to an instruction register. A first control circuit responds to source-codes to select the general registers having respective pieces of data to be compared. A first latch stores instruction data including a code for an operation to be performed by an arithmetic and logic unit (ALU) on the two pieces of data under the control of a second control circuit. A conditional code register stores a conditional code. representing the result of the ALU operation, and a second latch stores selection criteria for destination registers specified by the instruction. A selection circuit operates under the control of a third control circuit to sort the ALU output data of a third control circuit to the specific destination register in accordance with the selection criteria and the condition code. The instruction execution is completed within a single CPU cycle.

Abstract: A small size graphic microcomputer provided with a direction control circuit and a coordinate computing circuit, which allow for finer control over the direction in which a dot of interest is moving. The sequence of operations from the calculation of coordinates through address generation is carried out sequentially so that addresses in the drawing memory can be obtained at high speed in response to each output clock.

Abstract: A digital filter processing device includes at least a plurality of multipliers each for multiplying data signal by coefficient data, and an adder for adding together the multiplication results derived from the multipliers. The digital filter processing device further includes coefficient registers each for storing the coefficient data as is shifted so that a first effective digit of the coefficient data lies at the left end, shift-quantity registers provided in connection with the coefficient registers, and each for storing a quantity of shift equal to the shift quantity of the coefficient data, and barrel shifters each for shifting the digits of an output data from each of the multipliers by the shift quantity stored in each of the shift-quantity registers, in the opposite direction to that of the shift in each of the coefficient registers.

Abstract: An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced.