Abstract: An induction type transducer is formed to be a substrate 162 having a multilayer structure. The substrate 162 has a multilayer structure including six layers, a first layer 162a through sixth layer 162f. An exciting coil is formed at the first layer 162a. Detecting coils are formed at the second layer 162b and the third layer 162c. A wiring layer is formed at the fifth layer 162e at the opposite side of the scale from the core layer 161. A signal processing IC 166 is formed at the sixth layer 162f. A magnetic sheild layer, which insulates magnetic flux from the exciting coil, is formed at the fourth layer 162d between the exciting coil and the signal processing IC 166.

Abstract: An optical encoder is constructed by a reflection-type scale 1 and a sensor head 4. The sensor head 4 has an irradiation light source 2 and a sensor board 3. the sensor board 3 has a transparent substrate 30 on which light-receiving areas 5 for outputting displacement signals which have different phase with each other, and index gratings 6 for modulating the scale irradiating light are formed to be alternately arranged. The index gratings 6 are formed of the same material film as metal electrode of the light-receiving areas 5.

Abstract: Output of an encoder are sampled by A/D converters 11a and 11b to be converted to N bits A-phase and B-phase digital data DA and DB. In a look-up table memory 12, reference phase angle data of phase divisions and average gradient vectors of changes in phase angle data within the phase divisions are stored, the phase divisions being addressed by the high order NU bits of data DA and DB. An arithmetic circuit 13 determines a vector inner product of an average gradient vector and phase-interpolating data represented by the low order NL bits of the data DA and DB to add the resultant to a phase angle data, thereby outputting an interpolated phase angle data.

Abstract: A magnetic encoder that allows the power consumption to be reduced has a first member 1 magnetized at pitches .lambda. and a second member 2 disposed so as to be relatively movable to the first member 1. The second member 2 has at least four MR devices Ma1, Mb1, Ma2, and Mb2 with phases that differ from by .lambda./4 each. The MR devices Ma1, Mb1, Ma2, and Mb2 are connected as a bridge circuit. Thus, a displacement detecting circuit 30 that outputs two-phase sine wave signals INA and INB is structured. The detecting circuit 30 is intermittently activated by analog switches Sa1, Sb1, Sa2, and Sb2 driven by a first clock CK1. The output signals INA and INB of the detecting circuit 30 are sampled by sample hold circuits 41a and 41b, respectively. The sampled values are compared by comparators 42a and 42b, whereby binary data is obtained. The comparators 42a and 42b each have a bias circuit 44 that is intermittently driven by a second clock CK2.

Abstract: An interpolation circuit of an encoder of which dynamic accuracy is improved is disclosed. The phase angle data detecting circuit 1 detects to store the phase angle data PH for each of the first clock CK1. The phase angle data PH is input to the updating circuit 2 in which the current data CNT is subtracted from the subsequent phase angle data PH so as to be updated. The differential data DX is limited within an upper limit to be added to the current data CNT. The integrating circuit 3 integrates the differential data DELTA1, whose upper limit is predetermined, by the second clock CK2 to generate the carry signal QUADEN at each timing when the integrated value leads to the period ratio of CK1 to CK2. The two-phase square wave generating circuit 5 generates two-phase square wave signals at each timing of the carry signal QUADEN. The over-speed detecting circuit 6 monitors the differential data DX to generate the over-speed alarm signal OSALM under a predetermined condition.

Abstract: A data output encoder capable of having its state of retaining internal error information and self-diagnostic information reset without recourse to removing power or furnishing a dedicated signal line. A reset pulse generator monitors the changing status of an externally provided output request signal. When the signal status reaches a predetermined pattern, the reset pulse generator generates reset pulses that cause an RS flip-flop circuit to reset the state in which the internal error information and self-diagnostic information are retained.