Patents by Inventor Tetsuro Matsumoto
Tetsuro Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8274462Abstract: An electro-optical device includes a pixel that has an electro-optical element with a light transmittance that changes to a predetermined value in response to an applied voltage, which changes in response to the temperature. A light source irradiates light to the pixel. A driving unit includes a predetermined number of sub-fields having the same length in one frame. The driving unit provides either an on-voltage indicating light-on or an off-voltage indicating light-off to the pixel in each of the predetermined number of the sub-fields in response to the grayscale to be displayed. A temperature measuring unit measures the temperature and outputs a temperature signal. A time controlling unit controls the length of one sub-field on the basis of the temperature signal. A light intensity controlling unit controls the intensity of the light incident on the pixel on the basis of the temperature signal.Type: GrantFiled: August 17, 2009Date of Patent: September 25, 2012Assignee: Seiko Epson CorporationInventors: Tomoyuki Okuyama, Tetsuro Matsumoto
-
Publication number: 20110254497Abstract: An actuator includes an electrolyte membrane, first and second driving electrodes that are disposed on the opposite surfaces and that give a potential difference to the electrolyte membrane, a sensor that is formed on the electrolyte membrane and that detects a force acting on the electrolyte membrane, and a driving control circuit that supplies a drive voltage to the first and second driving electrodes on the basis of an instruction signal and a detection output of the sensor. The driving control circuit applies a PWM drive voltage with a duty ratio corresponding to a difference between the instruction signal and the detection output of the sensor across the first driving electrode and the second driving electrode.Type: ApplicationFiled: April 11, 2011Publication date: October 20, 2011Applicant: SEIKO EPSON CORPORATIONInventor: Tetsuro MATSUMOTO
-
Publication number: 20110203265Abstract: An actuator is equipped with a moveable part 160 that moves according to changes in an intake amount of air, a cylinder 140 that contains air and pumps the air through a fluid pipe 150 to the moveable part 160 according to pressure applied to the air, and a piston 130 that applies pressure to the air in the cylinder 140. Further, the actuator is equipped with a motor 100 that generates rotational force, and a screw 110 and a slide nut 120 that convert the rotational force to a force to move the piston 130. The air is enclosed in the moveable part 160, the cylinder 140 and the fluid pipe 150.Type: ApplicationFiled: February 17, 2011Publication date: August 25, 2011Applicant: SEIKO EPSON CORPORATIONInventor: Tetsuro MATSUMOTO
-
Publication number: 20110043546Abstract: A display drive circuit that performs digital driving for displaying an image of each one frame based on luminance data of a plurality of subframes is disclosed. The display drive circuit includes a conversion section that converts the luminance data having a plurality of bits indicating a luminance level of each of the plurality of subframes into data indicating the luminance level for pixels in a number greater than the number of the plurality of subframes, and a storage section that stores the data converted by the conversion section.Type: ApplicationFiled: August 19, 2010Publication date: February 24, 2011Applicant: SEIKO EPSON CORPORATIONInventor: Tetsuro MATSUMOTO
-
Patent number: 7872417Abstract: A diode chip is sealed by a glass material. There are provided a light emitting diode chip and a glass member in close contact with at least one portion of the surface of the light emitting diode chip. The glass member has a surface shape containing a curved surface at least a portion thereof. The curved surface is preferably a portion of a spherical surface or a spheroidal surface. The glass member has a surface shape containing a spherical portion and a flat portion, and the diode chip is preferably disposed on the flat portion.Type: GrantFiled: October 11, 2007Date of Patent: January 18, 2011Assignee: Asahi Glass Company, LimitedInventors: Nobuhiro Nakamura, Syuji Matsumoto, Hitoshi Onoda, Yutaka Segawa, Tetsuro Matsumoto, Hiroshi Usui
-
Publication number: 20100289731Abstract: An electro-optical device includes a temperature detecting unit that detects temperature, wherein the electro-optical device sets a number of sub-frames of plural sub-frames included in one frame according to the temperature detected by the temperature detecting unit and sets a luminance level of pixels in each of the plural sub-frames to at least a first level or a second level to perform gradation display.Type: ApplicationFiled: May 11, 2010Publication date: November 18, 2010Applicant: SEIKO EPSON CORPORATIONInventor: Tetsuro MATSUMOTO
-
Publication number: 20100039441Abstract: An electro-optical device includes a pixel that has an electro-optical element with a light transmittance that changes to a predetermined value in response to an applied voltage, which changes in response to the temperature. A light source irradiates light to the pixel. A driving unit includes a predetermined number of sub-fields having the same length in one frame. The driving unit provides either an on-voltage indicating light-on or an off-voltage indicating light-off to the pixel in each of the predetermined number of the sub-fields in response to the grayscale to be displayed. A temperature measuring unit measures the temperature and outputs a temperature signal. A time controlling unit controls the length of one sub-field on the basis of the temperature signal. A light intensity controlling unit controls the intensity of the light incident on the pixel on the basis of the temperature signal.Type: ApplicationFiled: August 17, 2009Publication date: February 18, 2010Applicant: SEIKO EPSON CORPORATIONInventors: Tomoyuki OKUYAMA, Tetsuro MATSUMOTO
-
Publication number: 20090261944Abstract: A server computer includes a receiving part for receiving a content and apparatus identification information of an apparatus that existed in a vicinity when the content was generated; an extracting part for extracting identification information corresponding to the apparatus identification information received by the receiving part by referring to a database in which the identification information is stored in association with the apparatus identification information; a storing part for storing the content and apparatus identification information received by the receiving part and the identification information extracted by the extracting part in an associated manner in the storage unit; and a first sending part for sending the content stored in the storage unit to another information processor corresponding to identification information received from outside when the identification information received from the outside matches the identification information stored in the storage unit.Type: ApplicationFiled: March 17, 2009Publication date: October 22, 2009Applicant: FUJITSU LIMITEDInventors: Shigeki FUKUTA, Tetsuro Matsumoto
-
Publication number: 20080136326Abstract: A diode chip is sealed by a glass material. There are provided a light emitting diode chip and a glass member in close contact with at least one portion of the surface of the light emitting diode chip. The glass member has a surface shape containing a curved surface at least a portion thereof. The curved surface is preferably a portion of a spherical surface or a spheroidal surface. The glass member has a surface shape containing a spherical portion and a flat portion, and the diode chip is preferably disposed on the flat portion.Type: ApplicationFiled: October 11, 2007Publication date: June 12, 2008Applicant: ASAHI GLASS COMPANY LIMITEDInventors: Nobuhiro Nakamura, Syuji Matsumoto, Hitoshi Onoda, Yutaka Segawa, Tetsuro Matsumoto, Hiroshi Usui
-
Patent number: 6919622Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: February 10, 2004Date of Patent: July 19, 2005Assignee: Renesas Technology Corp.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Publication number: 20040155323Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: ApplicationFiled: February 10, 2004Publication date: August 12, 2004Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Patent number: 6720208Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: December 19, 2002Date of Patent: April 13, 2004Assignee: Renesas Technology CorporationInventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Publication number: 20030127712Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: ApplicationFiled: December 19, 2002Publication date: July 10, 2003Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Patent number: 6531760Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: April 25, 2000Date of Patent: March 11, 2003Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Patent number: 6326681Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: January 13, 2000Date of Patent: December 4, 2001Assignee: Hitachi, LTDInventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Patent number: 6303982Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: January 30, 2001Date of Patent: October 16, 2001Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Patent number: 6204552Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: January 12, 2000Date of Patent: March 20, 2001Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Patent number: 6124629Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: October 8, 1998Date of Patent: September 26, 2000Assignee: Hitachi, Ltd.Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
-
Patent number: RE37377Abstract: An illumination device for a direct viewing type display element comprising a flat light guide; a light source set such that light is incident on a side portion of said flat light guide; a polarized light separating flat set on a first side of a light emitting side of the flat light guide for transmitting a p polarized light component and reflecting at least a portion of an s polarized light component with respect to a light ray substantially having a predetermined direction of incidence; and a light reflecting sheet disposed on a second side opposite to said light emitting side of the flat light guide in parallel with the light emitting site.Type: GrantFiled: January 30, 1998Date of Patent: September 18, 2001Assignee: Asahi Glass Company, Ltd.Inventors: Tomoki Gunjima, Yoshiharu Ooi, Masao Ozeki, Hiroaki Ito, Hiroshi Hasebe, Tetsuro Matsumoto, Yutaka Nakagawa
-
Patent number: RE38305Abstract: An illumination device for a direct viewing type display element comprising a flat light guide; a light source set such that light is incident on a side portion of said flat light guide; a polarized light separating flat set on a first side of a light emitting side of the flat light guide for transmitting a p polarized light component and reflecting at least a portion of an a polarized light component with respect to a light ray substantially having a predetermined direction of incidence; and a light reflecting sheet disposed on a second side opposite to said light emitting side of the flat light guide in parallel with the light emitting site.Type: GrantFiled: February 24, 2000Date of Patent: November 11, 2003Assignee: Asahi Glass Company Ltd.Inventors: Tomoki Gunjima, Yoshiharu Ooi, Masao Ozeki, Hiroaki Ito, Hiroshi Hasebe, Tetsuro Matsumoto, Yutaka Nakagawa