Abstract: A transfer (13) that changes a distribution ratio of torque to be transmitted to a wheel using an electric motor (43), is controlled by a TF-ECU (18). The TF-ECU (18) includes a driver circuit (200) that drives the electric motor (43), a current sensor (53) that detects an actual current of the electric motor (43), and a microcomputer (100) that calculates a target current (I*) corresponding to a desired distribution ratio of torque and performs current feedback control for calculating an operation amount (D) of the electric motor (43) so as to adjust an actual current (Ia) to the target current (I*), and then outputs to the driver circuit (200) a drive signal corresponding to the operation amount (D).

Abstract: A resistive random access memory includes a memory cell including a resistive element having a resistance which varies according to a write operation and stores data according to the resistance of the resistive element, a reference resistive element having a resistance set to a first value, a voltage line set to a first voltage during a first write operation in which the resistance of the resistive element is varied from a second value higher than the first value to the first value, and a voltage control circuit arranged between first ends of the two resistive elements. The voltage control circuit adjusts a value of the first voltage supplied from the voltage line so as to reduce a difference between currents flowing through the two resistive elements during the first write operation, and supply the adjusted first voltage to the first ends of the two resistive elements.

Abstract: A transfer (13) that changes a distribution ratio of torque to be transmitted to a wheel using an electric motor (43), is controlled by a TF-ECU (18). The TF-ECU (18) includes a driver circuit (200) that drives the electric motor (43), a current sensor (53) that detects an actual current of the electric motor (43), and a microcomputer (100) that calculates a target current (I*) corresponding to a desired distribution ratio of torque and performs current feedback control for calculating an operation amount (D) of the electric motor (43) so as to adjust an actual current (Ia) to the target current (I*), and then outputs to the driver circuit (200) a drive signal corresponding to the operation amount (D).

Abstract: A resistive random access memory includes a memory cell including a resistive element having a resistance which varies according to a write operation and stores data according to the resistance of the resistive element, a reference resistive element having a resistance set to a first value, a voltage line set to a first voltage during a first write operation in which the resistance of the resistive element is varied from a second value higher than the first value to the first value, and a voltage control circuit arranged between first ends of the two resistive elements. The voltage control circuit adjusts a value of the first voltage supplied from the voltage line so as to reduce a difference between currents flowing through the two resistive elements during the first write operation, and supply the adjusted first voltage to the first ends of the two resistive elements.

Abstract: A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.

Abstract: A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.

Abstract: A power amplifier includes: an input matching circuit including an inductor, the input matching circuit receiving an input signal and matching input impedances with each other; an amplifier amplifying the input signal that is passed through the input matching circuit; and a test circuit, wherein the test circuit includes: a capacitor connected to the inductor in the input matching circuit through first test switch; a negative resistance transistor provided between the inductor and first voltage source terminal with second test switch being interposed between the inductor and the negative resistance transistor; and a current source transistor provided between second voltage source terminal and the inductor, wherein, in testing, first and second test switches and the current source transistor are turned on to cause the inductor and the test circuit to form a oscillator and, in normal operation, first and second test switches and the current source transistor are turned off.

Abstract: A power amplifier includes: an input matching circuit including an inductor, the input matching circuit receiving an input signal and matching input impedances with each other; an amplifier amplifying the input signal that is passed through the input matching circuit; and a test circuit, wherein the test circuit includes: a capacitor connected to the inductor in the input matching circuit through first test switch; a negative resistance transistor provided between the inductor and first voltage source terminal with second test switch being interposed between the inductor and the negative resistance transistor; and a current source transistor provided between second voltage source terminal and the inductor, wherein, in testing, first and second test switches and the current source transistor are turned on to cause the inductor and the test circuit to form a oscillator and, in normal operation, first and second test switches and the current source transistor are turned off.

Abstract: The present invention is aimed at provision of a control apparatus for and a control method of controlling a motor for a vehicle driven by a driving circuit that operates according to a pulse width modulation (PWM) signal. Measurement of a duty of an output signal from the driving circuit is executed, and a difference between the measured duty and a target duty in a PWM control is then obtained to further execute setting of a correction value for correcting the target duty based on the above difference and to generate the PWM signal based on the corrected target duty.

Abstract: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those.

Abstract: A resistance memory element, which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, includes a pair of electrodes and a resistance memory layer sandwiched between the pair of electrodes and including a first layer of a first resistance memory material and a second layer of a second resistance memory material. The current value of the resistance memory element in the writing operation can be drastically decreased, and a nonvolatile semiconductor memory device of high integration and low electric power consumption can be formed.

Abstract: An NMOS transistor 14 having one end connected to one end of a resistance memory element 10 is provided, and when a voltage is applied to the resistance memory element 10 via the NMOS transistor 14 to switch the resistance memory element 10 from the low resistance state to the high resistance state, the gate voltage of the NMOS transistor 14 is set at a value which is equal to or greater than the total of the reset voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14 and is smaller than the total of the set voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14, whereby the voltage applied to the resistance memory element 10 is set at a value which is equal to or greater than the reset voltage and is smaller than the set voltage.

Abstract: A phase locked oscillator includes a voltage control oscillator and a phase comparator for detecting a phase difference between a phase of an output signal of the voltage control oscillator and a phase of a reference signal and controlling a voltage to be applied to the voltage control oscillator based on the detected phase difference. The phase locked oscillator also includes a delay control part configured to apply a variable delay time to the output signal of the voltage control oscillator and a delay time controlling part configured to control the delay time according to the detected phase difference.

Abstract: A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.

Abstract: The present invention is aimed at provision of a control apparatus for and a control method of controlling a motor for a vehicle driven by a driving circuit that operates according to a pulse width modulation (PWM) signal. Measurement of a duty of an output signal from the driving circuit is executed, and a difference between the measured duty and a target duty in a PWM control is then obtained to further execute setting of a correction value for correcting the target duty based on the above difference and to generate the PWM signal based on the corrected target duty.

Abstract: An NMOS transistor 14 having one end connected to one end of a resistance memory element 10 is provided, and when a voltage is applied to the resistance memory element 10 via the NMOS transistor 14 to switch the resistance memory element 10 from the low resistance state to the high resistance state, the gate voltage of the NMOS transistor 14 is set at a value which is equal to or greater than the total of the reset voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14 and is smaller than the total of the set voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14, whereby the voltage applied to the resistance memory element 10 is set at a value which is equal to or greater than the reset voltage and is smaller than the set voltage.

Abstract: A resistance memory element, which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, includes a pair of electrodes and a resistance memory layer sandwiched between the pair of electrodes and including a first layer of a first resistance memory material and a second layer of a second resistance memory material. The current value of the resistance memory element in the writing operation can be drastically decreased, and a nonvolatile semiconductor memory device of high integration and low electric power consumption can be formed.

Abstract: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those.

Abstract: A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.

Abstract: The present invention relates to semiconductor techniques using high dielectric oxides, more specifically to a thin film forming method for forming a thin film which is suitable as the electrodes of the oxide high dielectrics, a capacitor device using the oxide high dielectrics and a method for fabricating the same, an a semiconductor device using the capacitor device and a method for fabricating the semiconductor device. The capacitor device includes at least one of a pair of electrodes which is formed of a material containing titanium nitride of (200) orientation. This permits the capacitor device to have good quality even in a case that the capacitor dielectric film is formed of a high dielectric thin film grown in an oxidizing atmosphere. The capacitor device includes the electrodes of titanium nitride film, whereby the electrodes can be patterned by RIE, which much improves processing precision of the electrode patterning, and throughputs.