Abstract: An electric furnace extending method and apparatus for an optical fiber glass body alignment when connecting the extension use body and pulling member and making it possible to immediately start the extension after the fusing of the connection portion. A centering mechanism for centering the free end portion of the body and member on the furnace center side is provided between the furnace pipe of the electric furnace and grips of the extension use glass body and between the furnace pipe and the pulling member. The free end portion is centered by this centering mechanism, then the gripped sides of the body and member are fixed, the front ends of the two free end portions are abutted and fused and bonded at the highest temperature portion inside the electric furnace, then the highest temperature portion is moved to the extension portion of the glass body side and the extending of the glass body is commenced.

Abstract: An apparatus for producing an optical fiber porous glass preform using the VAD method which can stably produce a high quality optical fiber porous glass preform, wherein a target bar is only rotatably supported by a chuck and is not pulled upward, a lower tip of a soot body is detected by a laser and a photodetector, and a core burner and a cladding burner is lowered in response to the result detected. A tip position detecting drive and burners are synchronizingly lowered while the deposit of porous glass grows at the lower portion of the target bar.

Abstract: To increase the kinds of executable instructions of a microcomputer without increasing the number of bits (e.g. 8 bits) constituting one word or instruction, that is, without decreasing the execution speed or increasing the ROM usage, two or more instruction groups including instructions of different kinds, respectively, are provided operation modes are determined for the respective instruction groups; and the respective instruction groups to be executed are switched according to the respective operation modes. The microcomputer includes an instruction register, an execution control unit, a mode memory flip-flop, gates, two predecoders, a programmable logic array, an arithmetic logic unit, etc. The ordinary and special instruction groups can be selected in response to an interrupt entry signal and an interrupt return signal and a specific bit of an instruction, for instance.

Abstract: A power voltage drop detecting circuit includes VDD and ground terminals supplied with power voltage VD, a resistor connected at one end to the VDD terminal, a MOS transistor connected between the other end of the resistor and the ground terminal, and a CMOS inverter for producing an output signal according to a voltage at the junction between the resistor and the MOS transistor. The detecting circuit further includes a control pad connected to the control gate of the n-channel MOS transistor and supplied with control voltage VC at different levels in the test mode and detect modes, respectively.