Patents by Inventor Tetsurou Honda

Tetsurou Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8759119
    Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
  • Patent number: 8404496
    Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: March 26, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
  • Publication number: 20060279003
    Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.
    Type: Application
    Filed: May 24, 2006
    Publication date: December 14, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
  • Patent number: 7112889
    Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: September 26, 2006
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Yasuyuki Itoh, Tetsurou Honda, Kazuhiro Tashiro, Makoto Haseyama, Kenichi Nagashige, Yoshiyuki Yoneda, Hirohisa Matsuki
  • Patent number: 7062346
    Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. In the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the chips on a wafer is controlled based on a chip identification information formed on a wafer. The method includes the step of editing the chip identification information such that the chip identification information for chips having the same fabrication processing steps and chips formed on the same wafer can be read out successively. The method also includes the step of carrying out each of the fabrication processing steps based on the chip identification information formed on the wafer by reading out the chip identification information.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: June 13, 2006
    Assignee: Fujitsu Limited
    Inventors: Osamu Takagi, Tsuneo Iizuka, Tetsurou Honda, Takuya Honda
  • Patent number: 6862725
    Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer based on a chip identification information formed on the wafer, the method comprises at least two steps sharing the chip identification information before at least one of the two steps is carried out, wherein the steps are not immediately neighbored with each other in fabrication processing sequence.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: March 1, 2005
    Assignee: Fujitsu Limited
    Inventors: Osamu Takagi, Tsuneo Iizuka, Tetsurou Honda, Takuya Honda
  • Publication number: 20040225385
    Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer based on a chip identification information formed on the wafer, the method comprises at least two steps sharing the chip identification information before at least one of the two steps is carried out, wherein the steps are not immediately neighbored with each other in fabrication processing sequence.
    Type: Application
    Filed: June 2, 2004
    Publication date: November 11, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Osamu Takagi, Tsuneo Iizuka, Tetsurou Honda, Takuya Honda
  • Publication number: 20020017708
    Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer based on a chip identification information formed on the wafer, the method comprises at least two steps sharing the chip identification information before at least one of the two steps is carried out, wherein the steps are not immediately neighbored with each other in fabrication processing sequence.
    Type: Application
    Filed: September 20, 2001
    Publication date: February 14, 2002
    Applicant: Fujitsu Limited
    Inventors: Osamu Takagi, Tsuneo Iizuka, Tetsurou Honda, Takuya Honda