Patents by Inventor Tetsurou Toubou
Tetsurou Toubou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8525552Abstract: A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.Type: GrantFiled: July 30, 2012Date of Patent: September 3, 2013Assignee: Panasonic CorporationInventors: Takashi Ando, Keiichi Kusumoto, Kenji Shimazaki, Kazuyuki Nakanishi, Tetsurou Toubou
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Publication number: 20130027083Abstract: A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.Type: ApplicationFiled: July 30, 2012Publication date: January 31, 2013Inventors: Takashi Ando, Keiichi Kusumoto, Kenji Shimazaki, Kazuyuki Nakanishi, Tetsurou Toubou
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Patent number: 8261225Abstract: A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.Type: GrantFiled: March 1, 2010Date of Patent: September 4, 2012Assignee: Panasonic CorporationInventors: Tetsurou Toubou, Nana Okamoto, Junichi Yano
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Patent number: 8178905Abstract: In a layout structure capable of independent supply of a substrate or well potential from a power supply potential, further reduction in layout area is achieved. A reinforcing power supply cell is inserted in a cell line in which a plurality of cells are arranged in series. Each of the cells includes an impurity doped region for supplying a substrate or well potential NWVDD which is different from a positive power supply potential VDD to a p-type transistor arranging region. The reinforcing power supply cell includes a power supply impurity doped region to which an impurity doped region of an adjacent cell is electrically connected and a power supply wire provided in a wiring layer formed above the power supply impurity doped region and electrically connected to the power supply impurity doped region.Type: GrantFiled: January 11, 2008Date of Patent: May 15, 2012Assignee: Panasonic CorporationInventor: Tetsurou Toubou
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Patent number: 8159013Abstract: There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.Type: GrantFiled: February 24, 2009Date of Patent: April 17, 2012Assignee: Panasonic CorporationInventors: Hidetoshi Nishimura, Hiroyuki Shimbo, Tetsurou Toubou, Hiroki Taniguchi, Hisako Yoneda
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Publication number: 20100187699Abstract: There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.Type: ApplicationFiled: February 24, 2009Publication date: July 29, 2010Inventors: Hidetoshi Nishimura, Hiroyuki Shimbo, Tetsurou Toubou, Hiroki Taniguchi, Hisako Yoneda
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Publication number: 20100148235Abstract: A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.Type: ApplicationFiled: March 1, 2010Publication date: June 17, 2010Applicant: PANASONIC CORPORATIONInventors: Tetsurou Toubou, Nana Okamoto, Junichi Yano
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Patent number: 7685551Abstract: A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.Type: GrantFiled: June 28, 2006Date of Patent: March 23, 2010Assignee: Panasonic CorporationInventors: Tetsurou Toubou, Nana Okamoto, Junichi Yano
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Publication number: 20090138840Abstract: A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.Type: ApplicationFiled: January 26, 2009Publication date: May 28, 2009Applicant: PANASONIC CORPORATIONInventors: Miwa Ichiryu, Toshiyuki Moriwaki, Tetsurou Toubou
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Patent number: 7503026Abstract: A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.Type: GrantFiled: December 19, 2005Date of Patent: March 10, 2009Assignee: Panasonic CorporationInventors: Miwa Ichiryu, Toshiyuki Moriwaki, Tetsurou Toubou
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Publication number: 20080169868Abstract: In a layout structure capable of independent supply of a substrate or well potential from a power supply potential, further reduction in layout area is achieved. A reinforcing power supply cell is inserted in a cell line in which a plurality of cells are arranged in series. Each of the cells includes an impurity doped region for supplying a substrate or well potential NWVDD which is different from a positive power supply potential VDD to a p-type transistor arranging region. The reinforcing power supply cell includes a power supply impurity doped region to which an impurity doped region of an adjacent cell is electrically connected and a power supply wire provided in a wiring layer formed above the power supply impurity doped region and electrically connected to the power supply impurity doped region.Type: ApplicationFiled: January 11, 2008Publication date: July 17, 2008Inventor: Tetsurou TOUBOU
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Patent number: 7369618Abstract: A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor.Type: GrantFiled: May 19, 2005Date of Patent: May 6, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Keiichi Kusumoto, Toshiyuki Moriwaki, Tsuguyasu Hatsuda, Tetsurou Toubou
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Publication number: 20070004147Abstract: A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.Type: ApplicationFiled: June 28, 2006Publication date: January 4, 2007Inventors: Tetsurou Toubou, Nana Okamoto, Junichi Yano
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Publication number: 20060136848Abstract: A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.Type: ApplicationFiled: December 19, 2005Publication date: June 22, 2006Inventors: Miwa Ichiryu, Toshiyuki Moriwaki, Tetsurou Toubou
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Patent number: 6967866Abstract: A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.Type: GrantFiled: March 16, 2004Date of Patent: November 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akio Hirata, Toshiyuki Moriwaki, Tetsurou Toubou, Nana Okamoto, Mitsuaki Hayashi
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Publication number: 20050207504Abstract: A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor.Type: ApplicationFiled: May 19, 2005Publication date: September 22, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Keiichi Kusumoto, Toshiyuki Moriwaki, Tsuguyasu Hatsuda, Tetsurou Toubou
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Patent number: 6922443Abstract: A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor.Type: GrantFiled: November 15, 2000Date of Patent: July 26, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Keiichi Kusumoto, Toshiyuki Moriwaki, Tsuguyasu Hatsuda, Tetsurou Toubou
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Publication number: 20050149895Abstract: A delay library of high accuracy is efficiently generated within a short time period. To this end, a set-up time is calculated by static analysis with no consideration of a delay caused by a wire; the initial value of the search range for the next binary search cycle is set such that the set-up time is the median value of the search range (for example, the range of 0.5 ns is set); and correct set-up time ? is obtained using binary search based on the initial value of the search range.Type: ApplicationFiled: December 21, 2004Publication date: July 7, 2005Inventor: Tetsurou Toubou
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Publication number: 20040213029Abstract: A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.Type: ApplicationFiled: March 16, 2004Publication date: October 28, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Akio Hirata, Toshiyuki Moriwaki, Tetsurou Toubou, Nana Okamoto, Mitsuaki Hayashi