Abstract: A semiconductor storage device having a line-to-line burn-in function of main word lines, applying a stress voltage between the main word lines in a wafer burn-in state. In a wafer burn-in state, by a control circuit means, main word lines are divided to odd-numbered lines and even-numbered lines to be connected to an odd-numbered pad and an even-numbered pad respectively, and a stress voltage is applied directly between the odd-numbered pad and the even-numbered pad. By a row decoder being capable of control in both of an ordinary operation mode and a wafer burn-in operation mode, in a wafer burn-in state, main word lines are divided to odd-numbered lines and even-numbered lines to become selective state, and a stress voltage is applied between main word lines.

Abstract: During a burn-in test, a test mode signal TMRS is set to the H level, and word lines WL0 to WL3 can be activated by composite gates according to row address signals RA0 to RA3, respectively. Therefore, a potential difference and a high electric field are provided even between word lines WL0, WL2 during the burn-in test. Thus, the defect elimination rate during the burn-in test can be improved.

Abstract: A semiconductor storage device having a line-to-line burn-in function of main word lines, applying a stress voltage between the main word lines in a wafer burn-in state. In a wafer burn-in state, by a control circuit means, main word lines are divided to odd-numbered lines and even-numbered lines to be connected to an odd-numbered pad and an even-numbered pad respectively, and a stress voltage is applied directly between the odd-numbered pad and the even-numbered pad. By a row decoder being capable of control in both of an ordinary operation mode and a wafer burn-in operation mode, in a wafer burn-in state, main word lines are divided to odd-numbered lines and even-numbered lines to become selective state, and a stress voltage is applied between main word lines.

Abstract: In a semiconductor memory device a column decoder outputs column select signals which are in turn transmitted to a memory cell block via a transfer gate which turns on when a signal fed through a WBI pad is placed in the inactive state. Even-numbered column select lines are connected via a transfer gate to an even-numbered CSL pad, and odd-numbered column select lines are connected via the transfer gate to an odd-numbered CSL pad.

Abstract: A precharge control circuit controls on/off of transfer gates to set a signal level of a precharge control signal in accordance with a level of a control signal input to a precharge command input pad when a write recovery test signal is active. In a normal operation, the precharge control circuit deactivates the write recovery test signal to set the signal level of the precharge control signal in accordance with a combination of control signals. Consequently, the precharge operation can be started in accordance with an arbitrary control signal generated by an external memory tester or the like in a test mode, and thereby evaluation of a write recovery time can be executed.

Abstract: There is described a divided word line semiconductor storage device including a plurality of sub-word lines each having an open end and a main word line provided so as to be shared among the plurality of sub-word lines. The semiconductor storage device further includes a decoder which selectively supplies a high or low potential to a predetermined portion of each sub-word line according to whether or not the sub-word line corresponds to a designated address, and switching devices capable of connecting the open ends of the plurality of sub-word lines to a ground potential.

Abstract: A semiconductor memory device includes a memory cell array block (1; MB1 to MB16) having a first column group (area I) and a second column group (area II). The device also includes sense amplifiers (10-1, 10-2, 10-3 . . . ) provided for each column to detect and amplify a read-out voltage on associated columns. The device further includes a control circuit (20) for activating the sense amplifiers for the first column group and the sense amplifiers for the second column group at different timings to reduce peak current in sensing operation. The control circuit operates in response to a column designating signal to activate first the sense amplifiers for the column group including a column connecting thereto a selected memory cell. The column designating signal includes an externally applied column address bit. The column address bit is supplied to the device simultaneous with row address bits in an address multiplexing memory device.