Patents by Inventor Tetsushi Sakai

Tetsushi Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085822
    Abstract: An image forming apparatus includes an apparatus body, an image bearing member, and a process unit attached to the apparatus body, the process unit including a frame including a storage portion configured to store developer, a developer bearing member configured to supply developer to the image bearing member to develop an electrostatic latent image; and a circuit board attached to the frame, wherein the circuit board includes a light emitting portion configured to emit light, and a light receiving portion configured to receive the light emitted from the light emitting portion and having passed through an interior of the storage portion.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Tetsushi Uneme, Shinichi Nishida, Tsuyoshi Ogawa, Masahiro Suetsugu, Kengo Sakai
  • Publication number: 20070126034
    Abstract: An opening 35 is formed on an assembly having a silicon germanium layer 32, a silicon layer 33, and a silicon oxide layer 34 sequentially formed on a silicon basis material 31. An additional silicon oxide layer 36 is formed so as to cover the silicon oxide layer 34 and an inner surface of the opening 35. Then, the silicon germanium layer 32 is removed by etching, and a thermal oxidation treatment and an annealing treatment are sequentially performed on the silicon basis material 31 and the silicon layer 33 to form thermal oxidation layers 37 and 38. Then, a flat film 39 is formed for flat treatment to manufacture a semiconductor substrate 10 having an island part 12 made of silicon buried in an component 13 made of silicon oxide.
    Type: Application
    Filed: October 4, 2004
    Publication date: June 7, 2007
    Applicant: TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Tetsushi Sakai, Shunichiro Ohmi, Takashi Yamazaki
  • Publication number: 20070075317
    Abstract: A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer; a second insulating layer formed on the first single-crystal semiconductor layer and having a film thickness smaller than a film thickness of the first insulating layer; a second single-crystal semiconductor layer formed on the second insulating layer; a gate electrode formed on the second single-crystal semiconductor layer; and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
    Type: Application
    Filed: July 20, 2006
    Publication date: April 5, 2007
    Applicants: SEIKO EPSON CORPORATION, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Juri Kato, Hideaki Oka, Kei Kanemoto, Toshiki Hara, Tetsushi Sakai
  • Publication number: 20070018246
    Abstract: A semiconductor device includes a back gate electrode composed of a first single-crystal semiconductor layer formed on a first insulating layer, a second insulating layer formed on the first single-crystal semiconductor layer, a second single-crystal semiconductor layer formed on the second insulating layer and having a film thickness smaller than a film thickness of the first single-crystal semiconductor layer, a gate electrode formed on the second single-crystal semiconductor layer, and source and drain layers that are formed on the second single-crystal semiconductor layer and arranged on respective sides of the gate electrode.
    Type: Application
    Filed: June 7, 2006
    Publication date: January 25, 2007
    Applicants: SEIKO EPSON CORPORATION, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Juri Kato, Hideaki Oka, Kei Kanemoto, Toshiki Hara, Tetsushi Sakai
  • Patent number: 6229165
    Abstract: This invention provides a semiconductor device including a silicon layer, an insulating layer formed on the silicon layer, a first semiconductor device formed on the insulating film to convert light into an electric signal, and a second semiconductor device formed on the insulating film, wherein a silicon region is formed in the silicon layer to shield the second semiconductor device from light, and a through hole extending through the silicon layer except for the silicon region to input light to the first semiconductor device is formed in that portion of the silicon layer corresponding to the lower portions of the first and second semiconductor devices.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: May 8, 2001
    Assignee: NTT Electronics Corporation
    Inventors: Tetsushi Sakai, Nobuaki Ieda, Masayuki Ino, Shigeru Nakajima, Yukio Akazawa, Tsuneo Mano, Hiroshi Inokawa
  • Patent number: 5989981
    Abstract: A method of manufacturing an SOI substrate uses an SOI substrate having a first single-crystal silicon layer, an insulating layer formed on the first single-crystal silicon layer, and a second single-crystal silicon layer formed on the insulating layer. The surface of the second single-crystal silicon layer is thermally oxidized. The second single-crystal silicon layer is controlled to have a predetermined thickness by removing the thermally oxidized surface. This step controlling the second single-crystal silicon layer to have a predetermined thickness includes the step of eliminating, by annealing, a stacking fault formed by the thermal oxidation.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: November 23, 1999
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Sadao Nakashima, Terukazu Ohno, Toshiaki Tsuchiya, Tetsushi Sakai, Shinji Nakamura, Takemi Ueki, Yuichi Kado, Tadao Takeda
  • Patent number: 5189504
    Abstract: A semiconductor device of a MOS structure having a p-type gate electrode has a gate electrode including at least two layers consisting of a boron-doped polysilicon layer and a polysilicon layer doped with boron and an inert material. This inert material is nitrogen or carbon.
    Type: Grant
    Filed: January 30, 1992
    Date of Patent: February 23, 1993
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Satoshi Nakayama, Tetsushi Sakai
  • Patent number: 4920401
    Abstract: In a bipolar transistor, around the border line of the surface of a base region formed on a semiconductor substrate is formed a base electrode having a constant width of less than one micron and made of polycrystalline silicon. An island shaped emitter region is formed in the base region and an emitter electrode is formed on the surface of the emitter region. The emitter electrode is electrically isolated from the base electrode by an insulating film extending between the periphery of the emitter region and the base electrode.
    Type: Grant
    Filed: March 14, 1985
    Date of Patent: April 24, 1990
    Assignee: Nippon Telegraph & Telephone Public Corp.
    Inventors: Tetsushi Sakai, Yoshizi Kobayasi, Hironori Yamauchi, Yoshinobu Arita
  • Patent number: 4780427
    Abstract: A bipolar transistor includes collector, base and emitter regions. The collector region consists of a first semiconductor region of a first conductivity type and formed in contact with a surface of a semiconductor layer. The base region consists of a second semiconductor region of a second conductivity type formed within the collector region to be in contact with the surface of the semiconductor layer. The emitter region consists of a third semiconductor region of the first conductivity type formed within the base region to be in contact with the surface of the semiconductor layer. The transistor also includes collector, base, and emitter electrodes. The collector and base electrodes are connected to the collector and base regions at opposite edges of a single opening formed in a field insulating film covering the surface of the semiconductor layer. The collector and base electrodes consist of a conductor. The emitter electrode is connected to the emitter region and consists of a conductor.
    Type: Grant
    Filed: September 29, 1987
    Date of Patent: October 25, 1988
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tetsushi Sakai, Yoshiji Kobayashi
  • Patent number: 4531282
    Abstract: In a bipolar transistor, around the border line of the surface of a base region formed on a semiconductor substrate is formed a base electrode having a constant width of less than one micron and made of polycrystalline silicon. An island shaped emitter region is formed in the base region and an emitter electrode is formed on the surface of the emitter region. The emitter electrode is electrically isolated from the base electrode by an insulating film extending between the periphery of the emitter region and the base electrode.
    Type: Grant
    Filed: January 17, 1984
    Date of Patent: July 30, 1985
    Assignee: Nippon Telegraph and Telephone Public Corp.
    Inventors: Tetsushi Sakai, Yoshizi Kobayasi, Hironori Yamauchi, Yoshinobu Arita
  • Patent number: 4379001
    Abstract: In a semiconductor device such as a bipolar transistor and a field effect transistor of the type having a substrate, a doped polycrystalline silicon region selectively formed on the substrate and an insulating film overlying the polycrystalline silicon region, the region is shaped as mesa having side surfaces with a negative coefficient of gradient between the substrate and the top of the mesa.
    Type: Grant
    Filed: July 18, 1979
    Date of Patent: April 5, 1983
    Assignee: Nippon Telegraph & Telephone Public Corp.
    Inventors: Tetsushi Sakai, Yoshiji Kobayasi, Yousuke Yamamoto, Hironori Yamauchi
  • Patent number: 4188707
    Abstract: The semiconductor device comprises a semiconductor substrate, a polycrystalline silicon semiconductor body extending upwardly from a portion of the surface of the semiconductor substrate and containing an impurity at a substantially uniform concentration, and a metal electrode disposed on the top surface of the polycrystalline silicon semiconductor body. The metal electrode extends in the lateral direction beyond the periphery of the top surface of the polycrystalline silicon semiconductor body.
    Type: Grant
    Filed: July 11, 1977
    Date of Patent: February 19, 1980
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Masaru Asano, Tetsushi Sakai, Yoshio Sunohara
  • Patent number: 4128845
    Abstract: Inverted frustum shaped polycrystalline semiconductor layers are formed on the emitter and collector regions provided on one surface of a semiconductor substrate, and conductor layers are applied on the upper surfaces of the polycrystalline semiconductor surfaces to form emitter and collector electrodes thus providing a bipolar transistor for the integrated circuit device.
    Type: Grant
    Filed: July 19, 1976
    Date of Patent: December 5, 1978
    Assignee: Nippon Telegraph and Telephone Public Corp.
    Inventor: Tetsushi Sakai
  • Patent number: 4074300
    Abstract: In an insulated gate type field effect transistor comprising spaced source and drain regions, an insulating film between the source and drain regions and a gate electrode mounted on the insulating film, an inverted frustum shaped polycrystalline semiconductor layer is formed on the insulating film and the gate electrode is mounted on the polycrystalline semiconductor layer.
    Type: Grant
    Filed: February 13, 1976
    Date of Patent: February 14, 1978
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Tetsushi Sakai, Yutaka Sakakibara, Junichi Murota, Tsutomu Wada