Abstract: To provide a semiconductor integrated circuit including: a detection circuit that detects an occurrence of latch up and can be configured while adopting a layout configuration that suppresses the occurrence of latch up; and a recovery unit that enables a recovery from the latch up without cutting off a positive potential. The semiconductor integrated circuit includes: a n-channel MOS transistor 7 that is formed on a P-type region 3 on a semiconductor substrate; and a latch up detection circuit that detects an occurrence of latch up in the n-channel MOS transistor 7. The latch up detection circuit includes: a n-MOS transistor structure 12 in which a source 10 and a back gate 8 are connected in common with a source 5 and the back gate 8 of the n-channel MOS transistor 7; and an electric current detection unit 15 that detects an electric current flowing to a drain 9 of the n-MOS transistor structure 12.

Abstract: To provide a semiconductor integrated circuit including: a detection circuit that detects an occurrence of latch up and can be configured while adopting a layout configuration that suppresses the occurrence of latch up; and a recovery unit that enables a recovery from the latch up without cutting off a positive potential. The semiconductor integrated circuit includes: a n-channel MOS transistor 7 that is formed on a P-type region 3 on a semiconductor substrate; and a latch up detection circuit that detects an occurrence of latch up in the n-channel MOS transistor 7. The latch up detection circuit includes: a n-MOS transistor structure 12 in which a source 10 and a back gate 8 are connected in common with a source 5 and the back gate 8 of the n-channel MOS transistor 7; and an electric current detection unit 15 that detects an electric current flowing to a drain 9 of the n-MOS transistor structure 12.

Abstract: A semiconductor integrated circuit that suppresses steep changes of an output voltage when starting of a charge pump circuit to suppress transient displacement of output of a circuit block operating independently of the charge pump circuit is provided. A semiconductor integrated circuit has: a charge pump circuit which charges a first capacitor with an input voltage, transfers a charge accumulated in the first capacitor to a second capacitor, outputs, as an output voltage, a voltage of the second capacitor, and is capable of changing over a capability of charging the second capacitor; a first circuit block that receives a positive voltage and a grounding potential; and a second circuit block that receives the positive voltage and the output voltage of the charge pump. The semiconductor integrated circuit suppresses the charging capability by the charge pump circuit when starting of the charge pump circuit.

Abstract: A video output circuit that is operated at a low power supply voltage and capable of achieving reduced power consumption with a simple circuit configuration and a semiconductor integrated circuit incorporating the same are provided. The video signal output circuit includes a video signal input terminal 1, a clamp circuit 3 that is connected to the video signal input terminal 1, a voltage-current conversion circuit 4 that is connected to the clamp circuit 3, a current amplifier circuit 5 that is connected to the voltage-current conversion circuit 4 and a video signal output terminal 6 that is connected to the current amplifier circuit 5, wherein a resistor 8 is connected between the video signal output terminal 6 and a ground, a transmission line 9 is connected with the video signal output terminal 6, and a load resistor 10 having an equal resistance to the resistor 8 is connected between another end of the transmission line 9 and a ground. The clamp circuit 3 fixes a negative signal voltage.

Abstract: While a charge pump activation/deactivation control circuit is outputting a high level signal, MOS transistors for short-circuiting a flying capacitor are off, and the charge pump circuit operates normally. When the charge pump activation/deactivation control circuit outputs a low level signal, the MOS transistors for short-circuiting the flying capacitor are turned on, and the charge pump circuit is deactivated. Consequently, the voltages at the terminals of the flying capacitor are the same and the charge charged therein is discharged. Therefore, when the charge pump circuit is activated again, the initial amount of charge charged to the flying capacitor is zero. Consequently, no large current flows through an output capacitor in the first discharging cycle after the re-activation.

Abstract: A semiconductor integrated circuit that suppresses steep changes of an output voltage when starting of a charge pump circuit to suppress transient displacement of output of a circuit block operating independently of the charge pump circuit is provided. A semiconductor integrated circuit has: a charge pump circuit which charges a first capacitor with an input voltage, transfers a charge accumulated in the first capacitor to a second capacitor, outputs, as an output voltage, a voltage of the second capacitor, and is capable of changing over a capability of charging the second capacitor; a first circuit block that receives a positive voltage and a grounding potential; and a second circuit block that receives the positive voltage and the output voltage of the charge pump. The semiconductor integrated circuit suppresses the charging capability by the charge pump circuit when starting of the charge pump circuit.

Abstract: A semiconductor integrated circuit includes a charge pump circuit for stepping down or stepping up a voltage supplied from a single voltage supply VDD and outputting the voltage, by repeating an operation of charging a flying capacitor C1 and transferring charges stored in the flying capacitor to a storage capacitor C2. During the operation of the charge pump circuit, current supply for charging the flying capacitor is carried out by a current mirror operation. The semiconductor integrated circuit thus obtained by including the charge pump circuit is characterized in that rush current on startup of charge pumping is reduced and that output performance of a DC-CD converter is not impaired.

Abstract: A charge pump circuit includes terminals that are connectable with a flying capacitor and a charge capacitor, respectively, and driving transistors connected with the terminals, a power supply voltage, and a ground potential, for controlling the charging of the flying capacitor and the transfer of charges from the flying capacitor to the charge capacitor. By repeating alternately an operation of charging the flying capacitor and an operation of transferring charges stored in the flying capacitor to the charge capacitor according to control signals supplied to gates of the transistors, the power source voltage is stepped down or stepped up. At least one of the driving transistors has its gate to be connected to a driving buffer via an impedance element so that the control signal is supplied thereto via the driving buffer.

Abstract: While a charge pump activation/deactivation control circuit is outputting a high level signal, MOS transistors for short-circuiting a flying capacitor are off, and the charge pump circuit operates normally. When the charge pump activation/deactivation control circuit outputs a low level signal, the MOS transistors for short-circuiting the flying capacitor are turned on, and the charge pump circuit is deactivated. Consequently, the voltages at the terminals of the flying capacitor are the same and the charge charged therein is discharged. Therefore, when the charge pump circuit is activated again, the initial amount of charge charged to the flying capacitor is zero. Consequently, no large current flows through an output capacitor in the first discharging cycle after the re-activation.

Abstract: A semiconductor integrated circuit includes: a charge pumping circuit for generating a negative power supply voltage; an input portion for biasing an average value of an input signal at 0V; and a video signal output portion that operates with a positive/negative power supply utilizing the charge pumping circuit as a negative power supply to amplify the zero-biased signal, outputting signals of positive/negative polarity. A diode clamp circuit is connected to the input portion, and a maximum level of a voltage of the input signal on the negative side is clamped to a clamp voltage produced by the diode clamp circuit when the maximum level of the voltage of the input signal on the negative side is lower than the clamp voltage, thereby suppressing shrinkage of the output signal on the negative side. SYNC shrinkage in the video signal output portion during high luminance signal input is suppressed.

Abstract: In a semiconductor device such as a chip having both of an analog circuit and a digital circuit, each of a first power supply wiring (20) for supplying power to an I/O circuit (digital circuit) positioned in the semiconductor device and a third power supply wiring (30) for supplying power to an internal circuit (300) such as an analog circuit formed as a cell, which is a power supply wiring connected to the power supply wiring (20) and positioned in the semiconductor chip (200), is formed from a structure of a multilayer wiring. This lowers the synthesized impedance of these power supply wirings (20, 30) and reduces the influence of power supply noise resulting from the operation of the digital circuit on the analog circuit within the semiconductor chip.