Abstract: A non-transitory computer-readable recording medium storing an operation program for causing a computer to execute processing including: performing first learning with a high-precision data type in each of layers included in a learning model; calculating a number of bits to be used for quantization in each of the layers, based on a threshold value that corresponds to a first quantization error and a degree of attenuation by accumulation of quantization errors in a case where quantization is performed in the first learning; and repeatedly performing second learning that includes quantization in a data type based on the calculated number of bits for each of the layers until the second learning converges.

Abstract: An arithmetic device according to an embodiment includes a first operation unit that calculates a shared exponent bias value for shifting a dynamic range of a floating-point operation; a second operation unit that calculates a sum-of-product arithmetic result of a second number of bits larger than a first number of bits by performing arithmetic operations corresponding to a large number of elements on a first data set formed of a shared exponent bias value and an activation value of a floating point of the first number of bits, and a second data set formed of a shared exponent bias value and a weight of a floating point of the first number of bits; and a quantizer that updates the activation value by quantizing the number of bits of the sum-of-product arithmetic result from the second number of bits to the first number of bits.

Abstract: A TDC measures a time difference between delay time that is in accordance with voltage variations. A DCO 155 generates an oscillation signal having a cycle that is in accordance with an input signal. A frequency divider 156 generates a divided signal by dividing the oscillation signal. An adder 154 inputs, to the DCO 155, a signal obtained by adding a second signal that changes an oscillation cycle of the DCO 155 in accordance with the time difference measured by the TDC to a first signal that is in accordance with a phase difference between the divided signal and a reference signal. A control circuit 11 obtains a measurement time resolution of the TDC and matches a cycle modulation time resolution of the DCO 155 with the measurement time resolution of the TDC.

Abstract: A TDC measures a time difference between delay time that is in accordance with voltage variations. A DCO 155 generates an oscillation signal having a cycle that is in accordance with an input signal. A frequency divider 156 generates a divided signal by dividing the oscillation signal. An adder 154 inputs, to the DCO 155, a signal obtained by adding a second signal that changes an oscillation cycle of the DCO 155 in accordance with the time difference measured by the TDC to a first signal that is in accordance with a phase difference between the divided signal and a reference signal. A control circuit 11 obtains a measurement time resolution of the TDC and matches a cycle modulation time resolution of the DCO 155 with the measurement time resolution of the TDC.

Abstract: An electronic circuit is described including an oscillator generating an oscillating signal having a cycle responsive to an input signal, a voltage detector producing a detection signal responsive to a power supply voltage, a frequency divider generating a frequency-divided signal obtained by dividing a frequency of the oscillating signal by a frequency-division ratio responsive to the detection signal, and an adder obtaining a sum of a first signal and a second signal and to supply a signal responsive to the sum to the oscillator as the input signal. The first signal is responsive to a difference in phase between the frequency-divided signal and a reference signal, and the second signal is responsive to the detection signal. A related method is also described.

Abstract: A digital filter includes: a minimum-value holder that holds a minimum value of a measurement value inputted in the minimum-value holder and that outputs the minimum value as a held value; a limit-value circuit that receives the held value and that outputs the held value as a limit value in a case where the held value remains minimum during predetermined cycles; and an output controller that receives a maximum value, the measurement value, and the limit value, the maximum value defining an upper limit, outputs the measurement value as an output value if the measurement value is smaller than the limit value, and outputs the maximum value as the output value if the measurement value is equal to or larger than the limit value.

Abstract: An electronic circuit includes an oscillator configured to generate an oscillating signal having a cycle responsive to an input signal, a voltage detector configured to produce a detection signal responsive to a power supply voltage, a frequency divider configured to generate a frequency-divided signal obtained by dividing a frequency of the oscillating signal by a frequency-division ratio responsive to the detection signal, and an adder configured to obtain a sum of a first signal and a second signal and to supply a signal responsive to the sum to the oscillator as the input signal, the first signal being responsive to a difference in phase between the frequency-divided signal and a reference signal, and the second signal being responsive to the detection signal.

Abstract: A digital filter includes: a minimum-value holder that holds a minimum value of a measurement value inputted in the minimum-value holder and that outputs the minimum value as a held value; a limit-value circuit that receives the held value and that outputs the held value as a limit value in a case where the held value remains minimum during predetermined cycles; and an output controller that receives a maximum value, the measurement value, and the limit value, the maximum value defining an upper limit, outputs the measurement value as an output value if the measurement value is smaller than the limit value, and outputs the maximum value as the output value if the measurement value is equal to or larger than the limit value.

Abstract: A voltage regulator circuit includes: a first pulse generator configured to output a pulse whose level remains unchanged when an input signal of a first circuit is in a first period, and whose level changes from a second level to a first level when an edge of the input signal of the first circuit is detected after the first period; a second pulse generator configured to output a pulse from a time that the pulse output by the first pulse generator becomes the first level until a second period elapses; a first field-effect transistor having a source connected to a power supply potential node, and a drain connected to a power supply potential terminal of the first circuit; and a first switch configured to cause a potential at a gate of the first field-effect transistor to be a first potential.

Abstract: A variable delay circuit is provided which has a plurality of delay elements. The variable delay circuit comprises a delay time correction circuit for individually correcting a delay time on each of the plurality of delay elements to compensate for the variation in transistor performance among the plurality of delay elements.

Abstract: A voltage regulator circuit includes: a first pulse generator configured to output a pulse whose level remains unchanged when an input signal of a first circuit is in a first period, and whose level changes from a second level to a first level when an edge of the input signal of the first circuit is detected after the first period; a second pulse generator configured to output a pulse from a time that the pulse output by the first pulse generator becomes the first level until a second period elapses; a first field-effect transistor having a source connected to a power supply potential node, and a drain connected to a power supply potential terminal of the first circuit; and a first switch configured to cause a potential at a gate of the first field-effect transistor to be a first potential.

Abstract: A variable delay circuit is provided which has a plurality of delay elements. The variable delay circuit comprises a delay time correction circuit for individually correcting a delay time on each of the plurality of delay elements to compensate for the variation in transistor performance among the plurality of delay elements.

Abstract: A process for producing lipids having a high linoleic acid content is provided, wherein fungi of Pellicularia genus are cultivated in a medium of a carbohydrate or vegetable fiber as a carbon source. By separating the fungus body from the resulting culture and subjecting it to solvent extraction, the objective lipid is obtained.

Abstract: A poly-fatty acid or maleic anhydride-added fatty acid is manufactured by continuously passing a higher unsaturated fatty acid, alone or in combination with maleic anhydride, over a catalyst having phosphoric acid deposited on a synthetic silica-alumina carrier.

Abstract: A poly-fatty acid is manufactured by continuously passing a higher unsaturated fatty acid, over a catalyst having phosphoric acid deposited on a synthetic silica-alumina carrier.