Patents by Inventor Tetsuya Aita

Tetsuya Aita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11387421
    Abstract: The present invention aims to provide a solar cell having high durability against deterioration due to moisture ingress from the side surfaces. The solar cell 10 of the present invention includes: first and second electrodes 12 and 17; a perovskite layer 14 provided between the first and second electrodes 12 and 17 and containing an organic-inorganic perovskite compound (A) represented by the formula RMX3 where R is an organic molecule, M is a metal atom, and X is a halogen atom; and a side-surface-protecting layer 15 provided on a peripheral side of the perovskite layer 14 to coat at least part of a side surface of the perovskite layer 14, the side-surface-protecting layer 15 containing at least one selected from the group consisting of a metal halide (B1) and an organometal halide (B2) or containing an organohalide (C).
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 12, 2022
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Yuuichirou Fukumoto, Naohiro Fujinuma, Junichiro Anzai, Akinobu Hayakawa, Tetsuya Kurebayashi, Tetsuya Aita, Tomohito Uno
  • Publication number: 20200395494
    Abstract: The present invention aims to provide a method for producing a solar cell in which a continuous long scribed line is provided along the machine direction of a substrate so that failures due to breakage of the scribed line are reduced.
    Type: Application
    Filed: March 13, 2019
    Publication date: December 17, 2020
    Applicant: SEKISUI CHEMICAL CO., LTD.
    Inventors: Tetsuya AITA, Motohiko ASANO, Akinobu HAYAKAWA, Tomohito UNO, Tetsuya KUREBAYASHI, Shunsuke KUNUGI, Takeharu MORITA
  • Publication number: 20190379000
    Abstract: A first object of the present invention is to provide a solar cell having excellent photoelectric conversion efficiency and produced through a process including favorable scribing (e.g., mechanical patterning), and a method for producing the solar cell. A first aspect of the present invention provides a solar cell including, above a flexible substrate, an electrode, a transparent electrode, and a photoelectric conversion layer disposed between the electrode and the transparent electrode, the solar cell further including a hard film disposed between the flexible substrate and the electrode, the hard film containing a nitride, carbide, or boride, the nitride, carbide, or boride containing at least one element selected from the group consisting of titanium, zirconium, aluminum, silicon, magnesium, vanadium, chromium, molybdenum, tantalum, and tungsten.
    Type: Application
    Filed: March 2, 2018
    Publication date: December 12, 2019
    Applicant: SEKISUI CHEMICAL CO., LTD.
    Inventors: Tetsuya AITA, Akinobu HAYAKAWA, Motohiko ASANO, Mayumi YUKAWA, Tomohito UNO, Tetsuya KUREBAYASHI, Takeharu MORITA
  • Publication number: 20180212086
    Abstract: The present invention aims to provide a solar cell having high photoelectric conversion efficiency and excellent high-temperature, high-humidity durability. The present invention relates to a solar cell including at least: a photoelectric conversion layer; a hole transport layer; and an anode, the hole transport layer being disposed between the photoelectric conversion layer and the anode, the hole transport layer containing a polymer containing a halogen atom and an organic semiconductor component (1), the polymer containing a halogen atom having a structure that contains a halogen atom and an electron-withdrawing group bonded to a hetero atom.
    Type: Application
    Filed: July 29, 2016
    Publication date: July 26, 2018
    Applicant: SEKISUI CHEMICAL CO., LTD.
    Inventors: Tetsuya KUREBAYASHI, Tetsuya AITA, Mayumi YUKAWA, Motohiko ASANO, Tomohito UNO, Akinobu HAYAKAWA, Takeharu MORITA, Yuuichirou FUKUMOTO
  • Patent number: 9177974
    Abstract: An active matrix substrate includes a plurality of pixels arranged in a matrix, a plurality of capacitor lines (11b) extending in one of directions in which the pixels are aligned and in parallel to each other, a plurality of TFTs (5), one for each of the pixels, a protective film (16a) covering the TFTs (5), a plurality of pixel electrodes (18a) arranged in a matrix on the protective film (16a) and connected to the respective corresponding TFTs (5), and a plurality of auxiliary capacitors (6), one for each of the pixels. Each of the auxiliary capacitors (6) includes the corresponding capacitor line (11b), the corresponding pixel electrode (18a), and the protective film (16a) between the corresponding capacitor line (11b) and the corresponding pixel electrode (18a).
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto
  • Patent number: 9087749
    Abstract: An active matrix substrate (20a) includes a gate electrode (25) formed on an insulating substrate (10a), and a planarizing film (26) formed on the gate electrode (25) and made of a baked SOG material. The gate electrode (25) is a multilayer film including a first conductive film (27) formed on the insulating substrate (10a) and made of a metal except copper, a second conductive film (28) formed on the first conductive film (27) and made of copper, and a third conductive film (29) formed on the second conductive film (28) and made of the metal except copper.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 21, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Hara, Hirohiko Nishiki, Hisao Ochi, Tetsuya Aita, Tohru Okabe, Yuya Nakano
  • Patent number: 9076718
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: July 7, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
  • Patent number: 9024311
    Abstract: The present invention provides a thin film transistor including an oxide semiconductor layer (4) for electrically connecting a signal electrode (6a) and a drain electrode (7a), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer (6b) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer (6b) being in touch with the signal electrode (6a) and the oxide semiconductor layer (4) and separating the signal electrode (6a) from the oxide semiconductor layer (4). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: May 5, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Hara, Hirohiko Nishiki, Yoshimasa Chikama, Kazuo Nakagawa, Yoshifumi Ohta, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Miyajima, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20140367683
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Application
    Filed: September 5, 2014
    Publication date: December 18, 2014
    Inventors: Yoshifumi OHTA, Go MORI, Hirohiko NISHIKI, Yoshimasa CHIKAMA, Tetsuya AITA, Masahiko SUZUKI, Okifumi NAKAGAWA, Michiko TAKEI, Yoshiyuki HARUMOTO, Takeshi HARA
  • Patent number: 8865516
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: October 21, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
  • Patent number: 8829513
    Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01?Zn/(In+Zn)?0.22.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: September 9, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ota, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Patent number: 8823002
    Abstract: An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: September 2, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Tohru Okabe, Tetsuya Aita, Tsuyoshi Inoue, Yoshiyuki Harumoto, Takeshi Yaneda
  • Patent number: 8685803
    Abstract: A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: April 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20140014950
    Abstract: An active matrix substrate (20a) includes a gate electrode (25) formed on an insulating substrate (10a), and a planarizing film (26) formed on the gate electrode (25) and made of a baked SOG material. The gate electrode (25) is a multilayer film including a first conductive film (27) formed on the insulating substrate (10a) and made of a metal except copper, a second conductive film (28) formed on the first conductive film (27) and made of copper, and a third conductive film (29) formed on the second conductive film (28) and made of the metal except copper.
    Type: Application
    Filed: December 20, 2011
    Publication date: January 16, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Hara, Hirohiko Nishiki, Hisao Ochi, Tetsuya Aita, Tohru Okabe, Yuya Nakano
  • Patent number: 8582072
    Abstract: A method for manufacturing a display device 10 includes a substrate supporting step for supporting a plastic substrate 19 on a support substrate 50, with the plastic substrate 19 curved, and a thin film lamination step for laminating a plurality of thin films on the plastic substrate 19 supported on the support substrate 50.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: November 12, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Okabe, Takeshi Hara, Tetsuya Aita, Tsuyoshi Inoue
  • Patent number: 8530899
    Abstract: The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: September 10, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiyuki Harumoto, Takeshi Hara, Tohru Okabe, Takeshi Yaneda, Tetsuya Aita, Tsuyoshi Inoue, Michiko Takei
  • Publication number: 20130193430
    Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01?Zn/(In+Zn)?0.22.
    Type: Application
    Filed: March 29, 2010
    Publication date: August 1, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ota, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20130140552
    Abstract: A semiconductor device (100) according to the present invention includes: an oxide semiconductor layer (31) formed on an insulating layer (21), the oxide semiconductor layer (31) containing at least one element selected from the group consisting of In, Zn, and Sn; first and second sacrificial layers (41a) and (41b) formed, with an interspace from each other, on the oxide semiconductor layer (31); a second electrode (52a) formed in contact with an upper face of the first sacrificial layer (41a) and an upper face of the oxide semiconductor layer (31); and a third electrode (52b) formed in contact with an upper face of the second sacrificial layer (41b) and an upper face of the oxide semiconductor layer (31). The first and second sacrificial layers (41a) and (41b) contain an oxide having at least one element selected from the group consisting of Zn, Ga, Mg, Ca, and Sr.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 6, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshifumi Ohta, Takeshi Hara, Hinae Mizuno
  • Patent number: 8441016
    Abstract: Disclosed is a high-quality, efficiently manufacturable thin film transistor in which leakage current is minimized. The thin film transistor is provided with a semiconductor layer (34) that contains a channel region (34C) having a microcrystalline semiconductor; source and drain contact layers (35S and 35D) that contains impurities; a first source metal layer (36S) and a first drain metal layer (36D), and a second source metal layer (37S) and a second drain metal layer (37D). The end portion of the second metal source layer (37S) is located at a position receded from the end portion of the first metal source layer (36S) and the end portion of the second drain metal layer (37D) is located at a position receded from the end portion of the first drain metal layer (36D). The semiconductor layer (34) contains low concentration impurity diffusion regions formed near the end portions of the aforementioned source contact layer (35S) and drain contact layer (35D).
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: May 14, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tsuyoshi Inoue, Tohru Okabe, Tetsuya Aita, Michiko Takei, Yoshiyuki Harumoto, Takeshi Yaneda
  • Publication number: 20130105788
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor with excellent electric property and credibility, a thin film transistor having a channel layer formed of the oxide semiconductor, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, and includes Si, In, Zn, and O as constituent atoms.
    Type: Application
    Filed: May 6, 2010
    Publication date: May 2, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Takeshi Hara, Okifumi Nakagawa, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Kazuo Nakagawa, Hinae Mizuno