Patents by Inventor Tetsuya Akasu

Tetsuya Akasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Silicon wafer break pattern, silicon substrate, and method of generating silicon wafer break pattern
    Patent number: 6878609
    Abstract: In order to provide a silicon wafer break pattern that stabilizes the location and shape of the breaks at weak spots of the break pattern and that reduces waste, the through-holes of the break pattern is disposed along a scribe line, a first group of the through-holes are substantially disposed on only a first side of the scribe line, and a second group of the through-holes are substantially disposed on only a second side of the scribe line.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: April 12, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Akihisa Wanibe, Noriaki Okazawa, Yoshinao Miyata, Toshinao Shinbo, Tetsuya Akasu, Hisashi Akachi
  • Silicon wafer break pattern, silicon substrate, and method of generating silicon wafer break pattern
    Publication number: 20040121560
    Abstract: In order to provide a silicon wafer break pattern that stabilizes the location and shape of the breaks at weak spots of the break pattern and that reduces waste, the through-holes of the break pattern is disposed along a scribe line, a first group of the through-holes are substantially disposed on only a first side of the scribe line, and a second group of the through-holes are substantially disposed on only a second side of the scribe line.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akihisa Wanibe, Noriaki Okazawa, Yoshinao Miyata, Toshinao Shinbo, Tetsuya Akasu, Hisashi Akachi
  • Silicon wafer break pattern, silicon substrate
    Patent number: 6699552
    Abstract: In order to provide a silicon wafer break pattern that stabilizes the location and shape of the breaks at weak spots of the break pattern and that reduces waste, the through-holes of the break pattern is disposed along a scribe line, a first group of the through-holes are substantially disposed on only a first side of the scribe line, and a second group of the through-holes are substantially disposed on only a second side of the scribe line.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: March 2, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Akihisa Wanibe, Noriaki Okazawa, Yoshinao Miyata, Toshinao Shinbo, Tetsuya Akasu, Hisashi Akachi
  • Silicon wafer break pattern, silicon substrate, and method of generating silicon wafer break pattern
    Publication number: 20020164874
    Abstract: In order to provide a silicon wafer break pattern that stabilizes the location and shape of the breaks at weak spots of the break pattern and that reduces waste, the through-holes of the break pattern is disposed along a scribe line, a first group of the through-holes are substantially disposed on only a first side of the scribe line, and a second group of the through-holes are substantially disposed on only a second side of the scribe line.
    Type: Application
    Filed: April 16, 2002
    Publication date: November 7, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akihisa Wanibe, Noriaki Okazawa, Yoshinao Miyata, Toshinao Shinbo, Tetsuya Akasu, Hisashi Akachi