Abstract: An omnidirectional camera comprises a camera mounting frame of cylindrical hollow body, a plurality of horizontal camera units, each of which is provided on a horizontal plane orthogonal to a center line of the camera mounting frame and adapted to acquire an image in a horizontal direction. A vertical camera unit is provided so as to coincide with the center line of the camera mounting frame and adapted to acquire an image in a zenith direction. A ring-like GPS antenna is provided so as to surround the vertical camera unit.

Abstract: An omnidirectional camera comprises a camera mounting frame 6 of cylindrical hollow body, a plurality of horizontal camera units 7 each of which is provided on a horizontal plane orthogonal to a center line of the camera mounting frame 6 and adapted to acquire an image in a horizontal direction, a vertical camera unit 8 provided so as to coincide with the center line of the camera mounting frame 6 and adapted to acquire an image in a zenith direction, and a ring-like GPS antenna 19 provided so as to surround the vertical camera unit 8.

Abstract: A semiconductor device includes an interposer, a semiconductor chip mounted on the interposer, a first wiring pattern formed on the interposer, the first wiring pattern including a first contact coupled to a bonding wire from the semiconductor chip and a second contact coupled to an external terminal of the interposer, and a second wiring pattern formed adjacent to the first wiring pattern on the interposer, the second wiring pattern including a third contact coupled to another bonding wire from the semiconductor chip and a fourth contact coupled to another external terminal of the interposer. The first contact is closer to the semiconductor chip than the third contact.

Abstract: A timing analysis apparatus in an integrated logical circuit according to the present invention includes a jitter information generation unit for generating period jitter information of an operational clock in response to a power supply/ground noise, a jitter information storage unit for storing the generated period jitter information, and a timing analysis unit for performing a timing analysis of the integrated logical circuit based on the stored period jitter information.

Abstract: A semiconductor device suppresses a magnetic field caused by a current loop formed by a signal wiring and a return path wiring, to reduce transmission loss of a high-speed signal. The semiconductor device includes a signal current path connected from a signal pad to a first external terminal via a first bonding wire and an interposer, and a current return path connected from a second external terminal provided adjacent to the first external terminal to a second pad provided adjacent to the signal pad via the interposer essentially on the same plane. The signal current path and the current return path are positioned so that they intersect with each other, thereby reversing the direction of a loop through which the current flows, and as a result, magnetic fields caused by the current loop formed by the signal current path and the current return path cancel each other.

Abstract: In a method of delay calculation of relative timing paths of an integrated circuit, each of the paths contains at least one stage. The method is achieved by calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component; and by carrying out delay calculation of relative timing paths by using the on-chip variation depending on the systematic component and the on-chip variation depending on the random component.

Abstract: A timing analysis apparatus in an integrated logical circuit according to the present invention includes a jitter information generation unit for generating period jitter information of an operational clock in response to a power supply/ground noise, a jitter information storage unit for storing the generated period jitter information, and a timing analysis unit for performing a timing analysis of the integrated logical circuit based on the stored period jitter information.

Abstract: To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.

Abstract: In a method of delay calculation of relative timing paths of an integrated circuit, each of the paths contains at least one stage. The method is achieved by calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component; and by carrying out delay calculation of relative timing paths by using the on-chip variation depending on the systematic component and the on-chip variation depending on the random component.

Abstract: A design automation method is provided which reduces complication of design work resulting from individual verification of a plurality of objects to be verified, for example, electromigration and hot carrier effect. Limiting values are prepared individually for the objects to be verified while a combined limiting value is obtained by combining these limiting values. By the use of the combined limiting value, verification of reliability is performed for all the objects. Specifically, when applied to the electromigration and the hot carrier effect as the objects to be verified, verification can simultaneously be performed upon frequency limiting values for the electromigration and the hot carrier effect.

Abstract: In a method for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including the object logic cell, there are determined first delay data of the first signal from a first external input terminal to the object logic cell, first waveform slew data of the first signal to the object logic cell and first signal data indicating a frequency, duty ratio and jitter of the first signal and a second waveform slew data of the second signal to the object logic cell. A first portion of a first waveform of the first signal and a second portion of a second waveform of the second signal is calculated in time then it is determined whether the first portion of the first waveform overlaps the second portion of the second waveform.

Abstract: To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.

Abstract: In a method for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including the object logic cell, there are determined first delay data of the first signal from a first external input terminal to the object logic cell, first waveform slew data of the first signal to the object logic cell and first signal data indicating a frequency, duty ratio and jitter of the first signal and a second waveform slew data of the second signal to the object logic cell. A first portion of a first waveform of the first signal at the object logic cell is calculated in time based on the first delay data, and the first waveform slew data and the first signal data a second portion of a second waveform of the second signal at the object logic cell is calculated in time based on the second waveform slew data. Then, it is determined whether the first portion of the first waveform overlaps the second portion of the second waveform.