Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

Abstract: Some embodiments provide an apparatus including a semiconductor substrate having source regions and regions alternately arranged in a first direction; gate electrodes between the source regions and the drain regions; a first wiring layer including first conductive patterns covering the source regions and second conductive patterns covering the drain regions; first via conductors between the first conductive patterns and the source regions; second via conductors between the second conductive patterns and the drain regions; a second wiring layer over the first wiring layer, including third conductive patterns covering the first conductive patterns and fourth conductive patterns covering the second conductive patterns; third via conductors between the third conductive patterns and the first conductive patterns; and fourth via conductors between the fourth conductive patterns and the second conductive patterns.

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

Abstract: Embodiments of the disclosure include signal processing methods to precondition signals for transmission on a high speed bus. A preconditioning circuit is configured to receive a serialized data signal at an input node and to precondition the serialized output data signal to provide a preconditioned output signal at an output node. The pre-conditioning circuit may include a feedback circuit coupled between the input node and the output node that is configured to independently control both of a propagation delay between the output node and the input node and a magnitude of emphasis/de-emphasis applied to a signal at the output node for provision to the input node.

Abstract: Embodiments of the disclosure include signal processing methods to precondition signals for transmission on a high speed bus. A preconditioning circuit is configured to receive a serialized data signal at an input node and to precondition the serialized output data signal to provide a preconditioned output signal at an output node. The preconditioning circuit may include a feedback circuit coupled between the input node and the output node that is configured to independently control both of a propagation delay between the output node and the input node and a magnitude of emphasis/de-emphasis applied to a signal at the output node for provision to the input node.

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a logic circuit. A pre-emphasis control signal based on at least one of the pull-up and pull-down data activation signals is provided to control providing pre-emphasis having a timing based on a mode of operation.

Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a logic circuit. A pre-emphasis control signal based on at least one of the pull-up and pull-down data activation signals is provided to control providing pre-emphasis having a timing based on a mode of operation.

Abstract: The present invention aims at providing a novel indocyanine compound solving problems of conventionally used indocyanine green, such as solubility in water or physiological saline, a synthesis method and a purification method thereof, and a diagnostic composition including the novel indocyanine compound. Further, provided are a method for evaluating biokinetics of the novel indocyanine compound and a device for measuring biokinetics, and a method and a device for visualizing circulation of fluid such as blood in a living body, which utilize the diagnostic composition. Also, found are a novel indocyanine compound in which a hydrophobic moiety in a near-infrared fluorescent indocyanine molecule is included in a cavity of a cyclic sugar chain cyclodextrin to cover the hydrophobic moiety in the indocyanine molecule with the glucose, and a synthesis method and a purification method thereof.

Abstract: A general engine throttle apparatus includes a throttle body 12, a throttle valve 13, a throttle shaft 14, a driven gear 24, an electrically driven motor 15, and a detected body block 26. The throttle valve 13 opens and closes an intake air introduction hole 11. The throttle shaft 14 holds the throttle valve 13 and is rotatably supported by a holding hole 16 of the throttle body 12. The electrically driven motor 15 transmits a rotation operation force to the driven gear 24. The detected body block 26 is attached to another end part in an axial direction of the throttle shaft 14, and a state of the throttle shaft 14 is detected by a sensor. The driven gear 24 is integrally formed on one end side in the axial direction of the throttle shaft 14. The detected body block 26 is formed to have a maximum outer diameter that is smaller than a minimum inner diameter of the holding hole 16.

Abstract: A throttle apparatus includes a throttle body (12), a throttle valve (13), a throttle shaft (14), an electrically driven motor (15), a drive gear (23), a driven gear (24), a middle gear (25), and a sensor block (19). The middle gear (25) is held by the throttle body (12) such that a gear shaft is displaced from an imaginary straight line (V) connecting together a motor shaft and the throttle shaft (14). A gear arrangement projection part (34) that projects outward by a displacement amount of the middle gear (25) and a connector arrangement projection part (35) that projects to a same side as the gear arrangement projection part (34) at a position adjacent to a motor housing part (12b) side of the gear arrangement projection part (34) are formed on an outer surface of the throttle body (12).

Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Abstract: A general engine throttle apparatus includes a throttle body 12, a throttle valve 13, a throttle shaft 14, a driven gear 24, an electrically driven motor 15, and a detected body block 26. The throttle valve 13 opens and closes an intake air introduction hole 11. The throttle shaft 14 holds the throttle valve 13 and is rotatably supported by a holding hole 16 of the throttle body 12. The electrically driven motor 15 transmits a rotation operation force to the driven gear 24. The detected body block 26 is attached to another end part in an axial direction of the throttle shaft 14, and a state of the throttle shaft 14 is detected by a sensor. The driven gear 24 is integrally formed on one end side in the axial direction of the throttle shaft 14. The detected body block 26 is formed to have a maximum outer diameter that is smaller than a minimum inner diameter of the holding hole 16.

Abstract: A throttle apparatus includes a throttle body (12), a throttle valve (13), a throttle shaft (14), an electrically driven motor (15), a drive gear (23), a driven gear (24), a middle gear (25), and a sensor block (19). The middle gear (25) is held by the throttle body (12) such that a gear shaft is displaced from an imaginary straight line (V) connecting together a motor shaft and the throttle shaft (14). A gear arrangement projection part (34) that projects outward by a displacement amount of the middle gear (25) and a connector arrangement projection part (35) that projects to a same side as the gear arrangement projection part (34) at a position adjacent to a motor housing part (12b) side of the gear arrangement projection part (34) are formed on an outer surface of the throttle body (12).

Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.