Abstract: An information processing apparatus includes a secure area configured to execute a program in secret, and a security chip. The secure area conceals information related to the program, and requests the security chip to provide a blind signature with respect to the concealed information obtained by the concealing. The security chip calculates the blind signature and returns the blind signature to the secure area. The secure area acquires a signature with respect to the information related to the program from the blind signature.

Abstract: In a remote authorization control system including a resource access device, a resource management device, and an authentication device, the resource access device downloads an access control list from the authentication device onto a secure region in the resource access device. The resource access device downloads resources from the resource management device onto the secure region. The resource access device determines whether a user is allowed to use the resources based on the access control list when a resource use request is received from the user, and the resources access device allows the user to use the resources when the resources are usable.

Abstract: A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.

Abstract: In the semiconductor memory device of the present invention, a page buffer holds read data read from a memory cell selected from among a plurality of memory cell blocks, and outputs the held data in order. That is, read data is read not directly from the memory cell blocks but through the page buffer. A password control circuit compares a read password supplied during a read operation with an original password stored in advance, and outputs the result of comparison. A buffer control circuit changes the order the read data is output from the page buffer when the result of comparison is a mismatch. In other words, the page buffer outputs the read data in predetermined order when the read password is correct, and outputs the read data in random order when the read password is incorrect. This realizes security protection of the data written in the semiconductor memory device.

Abstract: A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.

Abstract: A semiconductor memory device which can quickly and certainly read out block valid/invalid information is provided. This semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, and a valid/invalid information storage unit which stores valid/invalid information of the respective memory cells. The valid/invalid information storage unit is disposed outside the memory cell array.

Abstract: A non-volatile semiconductor memory device includes a string of memory cells provided for units of a predetermined information storage region and having a plurality of rewritable non-volatile memory cells connected in series. The string of memory cells is divided into a plurality of groups of memory cells. The device further includes a plurality of switching elements each connected in parallel with a corresponding one of the divided groups of memory cells, and a control unit for controlling on/off operations of the plurality of switching elements. Owing to this configuration, even if an invalid block occurs, the memory cells can be utilized effectively as a whole without the need of making the whole block unavailable.

Abstract: A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.