Abstract: According to one embodiment, a sound absorption device includes: a first plate having a plurality of first holes; a second plate facing the first plate in a first direction; a first frame connecting the first plate and the second plate; and a third plate supported by the first frame so as to vibrate in the first direction within the first frame. A first space is formed in the first frame between the first plate and the third plate. A second space is formed in the first frame between the second plate and the third plate. The third plate includes a first portion and a second portion, the second portion having a higher vibration speed than the first portion.

Abstract: A method of designing an LSI layout at a stage of making an LSI layout plan for each of a plurality of LSI chips before entering into the design of masks, which includes judging whether or not all the LSI chips can be arranged on a single wafer along with other (nonelectronic) components, based on a given LSI chip size and referring to the information on the other components. An LSI an LSI chip yield per water and/or a manufacturing cost per LSI chip are calculated, whereby an LSI layout designer can quickly and easily, within a limited LSI development term, determine how much the LSI chip size can be downsized for economical production of the LSI chip, referring to the results of the above judgment and calculation.

Abstract: The invention provides a method of LSI layout which is used in the stage of making a LSI layout plan for each of a plurality of LSI chips before entering in the design of masks, wherein there are included a step of judging whether or not all the LSI chips can be arranged on a single wafer along with other objective components, based on a given LSI chip size and referring to the information on the other objective components, or a step of calculating a LSI chip yield per water and/or a manufacturing cost per LSI chip. Therefore, a LSI layout designer can make a quick decision with ease within a limited LSI development term, as to how much the LSI chip size is to be downsized for economical production of the LSI chip, referring to the results of the above judgement and calculation.

Abstract: A method of manufacturing a multilayer ceramic electronic component including a step of firing a ceramic green sheet laminate having internal electrodes containing at least one of palladium and silver, and a step of firing the ceramic green sheet laminate in a furnace having an oxygen partial pressure of not more than 5% in a temperature area exceeding 50.degree. C. during a temperature rise from 400.degree. C. to 1100.degree. C.

Abstract: A dielectric ceramic composition containing 0.3 to 5.0 parts by weight of an additive composed of at least one of SiO.sub.2, Li.sub.2 O and B.sub.2 O.sub.3 per 100 parts by weight of a main component expressed by the following composition formula:(1-x-y-z-t)BaTiO.sub.3 +xCaZrO.sub.3 +yMgO+zMnO+tRe.sub.2 O.sub.3,wherex.ltoreq.0.060.005.ltoreq.y.ltoreq.0.080.005.ltoreq.z.ltoreq.0.020.005.ltoreq.t.ltoreq.0.02.In the composition formula, Re indicates at least one of Y, Gd, Dy, Ho, Er and Yb.