Patents by Inventor Tetsuya Furukawa

Tetsuya Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117346
    Abstract: In an embodiment, an object of the present invention is to provide a double-stranded nucleic acid complex having a novel structure. In an embodiment, the present invention relates to a nucleic acid complex comprising a first nucleic acid strand and a second nucleic acid strand, wherein said first nucleic acid strand: (1) is capable of hybridizing to at least a part of a target transcriptional product; (2) has an antisense effect on the target transcriptional product; and (3) is a gapmer comprising a central region, and a 5? wing region and a 3? wing region, said second nucleic acid strand comprises at least one sugar-unmodified central region (first exposed region) consisting of one sugar-unmodified ribonucleoside or two or three contiguous sugar-unmodified ribonucleosides linked by an internucleoside bond, which is or are complementary to a part of said first nucleic acid strand, and said first nucleic acid strand is annealed to said second nucleic acid strand.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 11, 2024
    Applicants: National University Corporation Tokyo Medical and Dental University, Takeda Pharmaceutical Company Limited
    Inventors: Takanori Yokota, Tetsuya Nagata, Hiroki Yamada, Hideki Furukawa, Takatoshi Yogo, Kenichi Miyata, Akio Uchida, Naoki Tomita
  • Patent number: 11462556
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
  • Publication number: 20210028185
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Application
    Filed: October 15, 2020
    Publication date: January 28, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
  • Patent number: 10840257
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
  • Publication number: 20200066743
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Application
    Filed: February 11, 2019
    Publication date: February 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
  • Patent number: 6065995
    Abstract: Two cables containing electric wires are electrically connected via a connecting device. The device includes a plurality of electrical connection units arranged in parallel and linked via a flexible linking portion. Each of the electrical connection units includes a groove adapted for stacking an electric wire of a first cable and an electric wire of a second cable to be connected thereto. Each groove is mounted with a cutting element. When the electric wires are received in the groove, the cutting element cuts into the electric wires and contacts a wire core included in the electric wire. Adjacent electrical connection units are connected through a flexible linking portion. By virtue of this connecting device, the cables are easily connected on the installation site and generation of an excess length of the cable is avoided.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: May 23, 2000
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventor: Tetsuya Furukawa