Patents by Inventor Tetsuya Furukawa
Tetsuya Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117346Abstract: In an embodiment, an object of the present invention is to provide a double-stranded nucleic acid complex having a novel structure. In an embodiment, the present invention relates to a nucleic acid complex comprising a first nucleic acid strand and a second nucleic acid strand, wherein said first nucleic acid strand: (1) is capable of hybridizing to at least a part of a target transcriptional product; (2) has an antisense effect on the target transcriptional product; and (3) is a gapmer comprising a central region, and a 5? wing region and a 3? wing region, said second nucleic acid strand comprises at least one sugar-unmodified central region (first exposed region) consisting of one sugar-unmodified ribonucleoside or two or three contiguous sugar-unmodified ribonucleosides linked by an internucleoside bond, which is or are complementary to a part of said first nucleic acid strand, and said first nucleic acid strand is annealed to said second nucleic acid strand.Type: ApplicationFiled: October 9, 2020Publication date: April 11, 2024Applicants: National University Corporation Tokyo Medical and Dental University, Takeda Pharmaceutical Company LimitedInventors: Takanori Yokota, Tetsuya Nagata, Hiroki Yamada, Hideki Furukawa, Takatoshi Yogo, Kenichi Miyata, Akio Uchida, Naoki Tomita
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Patent number: 11462556Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: GrantFiled: October 15, 2020Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
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Publication number: 20210028185Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: ApplicationFiled: October 15, 2020Publication date: January 28, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
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Patent number: 10840257Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: GrantFiled: February 11, 2019Date of Patent: November 17, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
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Publication number: 20200066743Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: ApplicationFiled: February 11, 2019Publication date: February 27, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
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Patent number: 6065995Abstract: Two cables containing electric wires are electrically connected via a connecting device. The device includes a plurality of electrical connection units arranged in parallel and linked via a flexible linking portion. Each of the electrical connection units includes a groove adapted for stacking an electric wire of a first cable and an electric wire of a second cable to be connected thereto. Each groove is mounted with a cutting element. When the electric wires are received in the groove, the cutting element cuts into the electric wires and contacts a wire core included in the electric wire. Adjacent electrical connection units are connected through a flexible linking portion. By virtue of this connecting device, the cables are easily connected on the installation site and generation of an excess length of the cable is avoided.Type: GrantFiled: November 12, 1998Date of Patent: May 23, 2000Assignee: Sumitomo Wiring Systems, Ltd.Inventor: Tetsuya Furukawa