Abstract: A serial-parallel converter/encoder unit 11 inputs a transmission symbol data at a transmission symbol rate that is one-Nth of a base-point symbol rate. A precoder/collator 13 creates a transmission symbol waveform at the base-point symbol rate. The transmission symbol waveform becomes a transmission signal after passing through a roll-off filter 14 with a band corresponding to the base-point symbol rate and a modulator 15. A reception signal demodulated by a demodulator 33 is input to a fractionally-spaced equalizer 38 that operates at the base-point symbol rate and is forcibly equalized at the transmission symbol rate by using a reference signal. A level of a signal output from the fractionally-spaced equalizer 38 at the transmission symbol rate is determined by a level determining unit 39 and becomes a reception symbol data by a sawtooth-function output unit 40.

Abstract: A signal transmission apparatus of the invention comprises: a correlator 12 for shaping a spectrum of a signal; and a precoder 12 disposed on a previous stage of the correlator and including an adder which subtracts an output signal of a feedback filter from an input signal, a modulo arithmetic unit which inputs an output signal of the adder and executes modulo arithmetic operation, and the feedback filter which inputs an output signal of the modulo arithmetic unit and is provided with a transfer function obtained by subtracting 1 from a transfer function of the correlator. The correlator may be IIR filter means having a desired notch characteristic. By disposing a correlator which can freely shape a transmission signal spectrum containing a deep notch and suppress only a specified band on a receiving side, the suppression of an external noise can also be realized.

Abstract: A transmitting circuit 10 converts transmission data to a multilevel analog signal suitable for transmission. The multilevel analog signal is output to a cable 21 via an amplifier and a hybrid circuit 12. In the transmitting circuit 10, a waveform which compensates waveform deterioration at the cable 21 is generated. A reception signal from the cable 21 is input to a mixer 14 via the hybrid circuit 12 and an amplifier 13. The mixer 14 mixes the reception signal and a cancel signal output from a cancel signal generation circuit 17 so as to remove undesired signals. In a receiving circuit 15, the signal output from the mixer 14 is sampled by use of a plurality of sample-hold circuits, and subjected to analog sum-of-product computation which is performed by a matrix circuit for distortion compensation. Subsequently, the sampled signals are converted to digital signals.

Abstract: A power consumption controlling apparatus controls power consumption of a high frequency amplifier to reduce the power consumption by adjusting a power supply voltage and a bias voltage of the high frequency amplifier which amplifies a high frequency transmitting signal. The power consumption controlling apparatus includes: a receiving circuit for receiving the high frequency transmitting signal amplified by the high frequency amplifier; an evaluating section for evaluating whether or not a receiving signal obtained from the receiving circuit satisfies a predetermined quality; and an adjusting section for adjusting the power supply voltage and the bias voltage in a range in which the receiving signal evaluated by the evaluating section satisfies the predetermined quality.

Abstract: It is an object of the present invention to realize a network system which can quickly detect a virus and tends not to be a new cause of vulnerability. A packet data comparator disclosed by the present invention branches inputted packet data into three branches, and includes an additional pattern matching unit which compares the branched packet data with a part of stored data and performs matching with collation patterns stored in a rewritable storage area, a fixed pattern matching unit which compares the branched packet data with the part of the stored data and performs the matching with a logical operation which has been configured with known collation patterns, a notification packet matching unit which compares the branched packet data with the part of the stored data and finds a notification packet, and an identity detection aggregation unit which aggregates results from the respective matching units.

Abstract: A status communication device includes a housing, at least one measuring unit, at least one state displaying unit, a transmitting unit, a receiving unit, a data selecting unit, and a state display controlling unit. The at least one measuring unit measures biological data of a user and an ambient state of the housing. The at least one state displaying unit displays a state of the user or the ambient state of the housing. The transmitting unit transmits first measurement-related data to at least one external device. The first measurement-related data is measurement data measured by the measuring unit or data based on the measurement data. The receiving unit receives second measurement-related data from at least one external device. The data selecting unit selects one state corresponding to the second measurement-related data to display with the state displaying unit if the receiving unit receives a plurality of the second measurement-related data within a prescribed interval.

Abstract: A method for designing a mask pattern realizes shortening the ever-growing time for the OPC treatment, decreases the fabrication TAT of a semiconductor device and cuts cost. A method for fabricating a semiconductor device uses the mask pattern designed. This invention performs the OPC treatment in advance on a cell library constituting the basic configuration of a semiconductor circuit pattern and prepares a semiconductor chip using the cell library that has undergone the OPC treatment.

Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

Abstract: A mask pattern designing method capable of achieving the reduction in the increasing OPC processing time, shortening the manufacture TAT of a semiconductor device, and achieving the cost reduction is provided. An OPC (optical proximity correction) process at the time when a cell is singularly arranged is performed to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance, and a semiconductor chip is produced using the cell library pattern to which the OPC process has been performed. At this time, since the cell library pattern which has been OPC-processed in advance is influenced by the cell library patterns around it, the correction process thereof is performed to the end portions of the patterns near the cell boundary. As particularly effective OPC correction means, the genetic algorithm is used.

Abstract: A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.

Abstract: A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.

Abstract: A necessary number of initial stage element circuits, intermediate stage element circuits, and final stage element circuits are connected in cascade and combined in parallel arrangement simultaneously. The partial sum output data on the element circuits is synchronized with the inner partial sum data. In this way, it is possible to configure a high-speed high-order and high-precision FIR filter, i.e., a large-scale digital filter. Thus, it is possible to manufacture a high-order and high-precision FIR filter capable of high-speed operation of 2 GHz or above at a low cost.

Abstract: A data compression method uses a template. In the template, the template optimizing is performed by an artificial intelligent technique (such as a genetic algorithm). The artificial intelligent techniqiue is applied to segments defined by diving input data into uniform segment units. The compression method contributes to enhancing the prediction accuracy. The data is compressed using the results of optimization, and a database is updated to improve the compression efficiency and speed of the subsequent processings. By updating a database by using an optimized template, a template for improving the prediction accuracy is obtained quickly without applying any artificial intelligent technique.

Abstract: A bus driving device is provided with a driver circuit for driving a bus line thereof. The driver circuit includes an MOS transistor whose well is separated from other circuits. Further, the bus driving device is provided with a voltage control section for adjusting a well voltage, in accordance with a level of a signal in the bus line. With this bus driving device, a threshold voltage of the MOS transistor is set at a predetermined target value.

Abstract: A semiconductor chip is manufactured using a cell library pattern obtained by performing OPC (optical proximity correction) process at the time of a cell single arrangement to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance. A plurality of cell libraries are arranged to design a mask pattern and a correction amount of OPC performed to the cell libraries is changed with taking into account the influence of a pattern of cell libraries arranged around a target cell. Further, a cell group with the same arrangement of surrounding cells including the target cell is extracted and is registered as a cell set, and a cell set with the same cell arrangement as that of the registered cell set is produced by copying without re-calculating OPC inside the cell set.

Abstract: A transmitting circuit 10 converts transmission data to a multilevel analog signal suitable for transmission. The multilevel analog signal is output to a cable 21 via an amplifier and a hybrid circuit 12. In the transmitting circuit 10, a waveform which compensates waveform deterioration at the cable 21 is generated. A reception signal from the cable 21 is input to a mixer 14 via the hybrid circuit 12 and an amplifier 13. The mixer 14 mixes the reception signal and a cancel signal output from a cancel signal generation circuit 17 so as to remove undesired signals. In a receiving circuit 15, the signal output from the mixer 14 is sampled by use of a plurality of sample-hold circuits, and subjected to analog sum-of-product computation which is performed by a matrix circuit for distortion compensation. Subsequently, the sampled signals are converted to digital signals.